SH7713 datasheet(102/904 Pages) RENESAS

номер детали	SH7713

подробное описание детали	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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производитель	RENESAS [Renesas Technology Corp]

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Section 2 CPU

Rev.1.50 Aug. 30, 2006 Page 62 of 860

REJ09B0288-0150

Table 2.10

Branch Instructions

Instruction

Instruction Code

Operation

Privileged

Mode

Cycles

T Bit

label

10001011dddddddd

If T

= 0, disp × 2 + PC → PC;

if T

= 1, nop



3/1*



BF/S

label

10001111dddddddd

Delayed branch,

if T

= 0, disp × 2 + PC → PC;

if T

= 1, nop



2/1*



label

10001001dddddddd

If T

= 1, disp × 2 + PC → PC;

if T

= 0, nop



3/1*



BT/S

label

10001101dddddddd

Delayed branch,

if T

= 1, disp × 2 + PC → PC;

if T

= 0, nop



2/1*



BRA

label

1010dddddddddddd

Delayed branch, disp

× 2 + PC

→ PC



BRAF

0000mmmm00100011

Delayed branch,Rm + PC

→ PC 



BSR

label

1011dddddddddddd

Delayed branch, PC

→ PR, disp

× 2 + PC → PC



BSRF

0000mmmm00000011

Delayed branch, PC

→ PR, Rm

+ PC

→ PC



JMP

@Rm

0100mmmm00101011

Delayed branch, Rm

→ PC



JSR

@Rm

0100mmmm00001011

Delayed branch, PC

→ PR, Rm

→ PC



RTS

0000000000001011

Delayed branch, PR

→ PC



Note:

One state when the branch is not executed.

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