M16CSLASH1N datasheet(231/238 Pages) RENESAS

231 / 238 page

Rev.1.00

Oct 20, 2004

page 219 of 222

M16C/1N Group

REJ090007-0100Z

20. Precautionary Notes in Using the Device

20.9 Flash Memory Version

20.9.1 Functions to Prevent Flash Memory from Rewriting

ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316,

0FFFF716, and 0FFFFB16. If wrong data are written to these addresses, the flash memory cannot

be read or written in standard serial I/O mode and CAN I/O mode.

The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the

flash memory cannot be read or written in parallel I/O mode.

In the flash memory version of microcomputer, these addresses are allocated to the vector ad-

dresses (H) of fixed vectors.

20.9.2 Stop Mode

When entering stop mode, the following settings are required:

• Set the CM10 bit to "1" (stop mode) after setting FMR01 bit to "0" (CPU rewrite mode disable).

• Execute the instruction to set the CM10 bit to "1" (stop mode) and then the JMP.B instruction.

Example program

BSET

0, CM1

; Stop mode

JMP.B

L1:

Program after exiting from stop mode

20.9.3 Wait Mode

When entering wait mode, set the FMR01 bit in the FMR0 register to "0" (CPU rewrite mode dis-

abled) before executing the WAIT instruction.

20.9.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode

If the CM05 bit is set to "1" (main clock stopped), do not execute the following commands:

• Program

• Block erase

• Erase all unlocked blocks

• Lock bit program

20.9.5 Writing Command and Data

Write commands and data to even addresses in the user ROM area.

20.9.6 Program Command

By writing "xx4016" in the first bus cycle and data to the write address in the second bus cycle, an

auto program operation (data program and verify) will start. The address value specified in the first

bus cycle must be the same even address as the write address specified in the second bus cycle.

20.9.7 Operation Speed

Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to clock

frequency of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the

PM17 bit in the PM1 register to "1" (with wait state).

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