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M16C/1N датащи(PDF) 227 Page - Renesas Technology Corp |
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M16C/1N датащи(HTML) 227 Page - Renesas Technology Corp |
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227 / 238 page ![]() Rev.1.00 Oct 20, 2004 page 215 of 222 M16C/1N Group REJ090007-0100Z 20. Precautionary Notes in Using the Device Figure 20.4 When Polling Period of CPU is 3fCAN or Longer Figure 20.3 With a Wait Time of 3fCAN Before CPU Read Figure 20.2 When Updating Period of CAN Module Matches Access Period from CPU fCAN : When the CAN module’s State_Reset bit updating period matches the CPU’s read period, it does not enter reset mode, for the CPU read has the higher priority. CPU read signal CPU reset signal Updating period of CAN module C0STR register b8: State_Reset bit 0: CAN operation mode 1: CAN reset/initial- ization mode : Updated without fail in period of 3fCAN Wait time CPU read signal CPU reset signal Updating period of CAN module C0STR register b8: State_Reset bit 0: CAN operation mode 1: CAN reset/initial- ization mode 4fCAN CPU read signal CPU reset signal Updating period of CAN module C0STR register b8: State_Reset bit 0: CAN operation mode 1: CAN reset/initial- ization mode : When the CAN module’s State_Reset bit updating period matches the CPU’s read period, it does not enter reset mode, for the CPU read has the higher priority. : Updated without fail in period of 4fCAN |
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