M16CSLASH1N datasheet(188/238 Pages) RENESAS

188 / 238 page

Rev.1.00

Oct 20, 2004

page 176 of 222

M16C/1N Group

19. Flash Memory Version

REJ09B0007-0100Z

Note 1: Once any of these bits is cleared to "0", it cannot be set back to "1". If a memory block that contains the

ROMCP register is erased, the ROMCP register is set to ’FF16’.

Note 2: If the ROMCR bits are set to ’002’ when the ROMCR bits are other than ’002’ and the ROMCP1 bits are oth-

er than ’112’, ROM code protect level 1 is removed. However, because the ROMCR bits cannot be modified

during parallel I/O mode, they need to be modified in standard serial I/O or other modes.

Note 3: If the ROMCR bits are set to other than ’002’ and the ROMCP1 bits are set to other than ’112’ (ROM code

protect enabled), the flash memory is disabled against reading and rewriting in parallel I/O mode.

Note 4: The ROMCP1 bits are effective when the ROMCR bits are ’012

’, ’102’, or ’112’.

Symbol

Address

Value when shipped

ROMCP

0FFFFF16

FF16 (Note 1)

ROM code protect control address

Bit name

Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

0 0 : Removes protect

0 1 :

1 0 :

1 1 :

0 0 :

0 1 :

1 0 :

1 1 : Protect disabled

ROM code protect reset bit

(Note 1, 2)

ROM code protect level

1 set bit (Note 1, 3, 4)

ROMCR

ROMCP1

b5 b4

b7 b6

Reserved bit

Set this bit to "1"

Enables ROMCP1 bit

}

Protect enabled

}

(b3-b0)

Reset vector

Watchdog timer vector

Single step vector

Address match vector

BRK instruction vector

Overflow vector

Undefined instruction vector

ID7

ID6

ID5

ID4

ID3

ID2

ID1

DBC vector

UART0 receive vector

0FFFFC16 to 0FFFFF16

0FFFF816 to 0FFFFB16

0FFFF416 to 0FFFF716

0FFFF016 to 0FFFF316

0FFFEC16 to 0FFFEF16

0FFFE816 to 0FFFEB16

0FFFE416 to 0FFFE716

0FFFE016 to 0FFFE316

0FFFDC16 to 0FFFDF16

4 bytes

Address

Figure 19.2 ROMCP register

Figure 19.3 ID code store addresses

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