M16CSLASH1N datasheet(130/238 Pages) RENESAS

130 / 238 page

Rev.1.00

Oct 20, 2004

page 118 of 222

M16C/1N Group

13. Serial I/O

REJ09B0007-0100Z

Item

Specification

• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected

• Start bit: 1 bit

• Parity bit: Odd, even, or nothing as selected

• Stop bit: 1 bit or 2 bits as selected

• When internal clock is selected (bit 3 at addresses 00A016, 00A816 = "0"):

fi/16(n+1) (Note 1) fi = f1, f8, f32, fC

• When external clock is selected (bit 3 at addresses 00A016 = "1"):

fEXT/16(n+1) (Note 1) (Note 2)

• To start transmission, the following requirements must be met:

- Transmit enable bit (bit 0 at addresses 00A516, 00AD16) = "1"

- Transmit buffer empty flag (bit 1 at addresses 00A516, 00AD16) = "0"

• To start reception, the following requirements must be met:

- Receive enable bit (bit 2 at addresses 00A516, 00AD16) = "1"

- Start bit detection

• When transmitting

- Transmit interrupt cause select bits (bits 0,1 at address 00B016) = "0":

Interrupts requested when data transfer from UARTi transfer buffer register

to UARTi transmit register is completed

- Transmit interrupt cause select bits (bits 0, 1 at address 00B016) = "1":

Interrupts requested when data transmission from UARTi transfer register is

completed

• When receiving

- Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

• Overrun error (Note 3)

This error occurs if the serial I/O started receiving the next data before read-

ing the UARTi receive buffer register and the bit one before the last stop bit

of the next data

• Framing error

This error occurs when the number of stop bits set is not detected

• Parity error

This error occurs when if parity is enabled, the number of 1’s in parity and

character bits does not match the number of 1’s set

• Error sum flag

This flag is set (= 1) when any of the overrun, framing, and parity errors is

encountered

• RxD1 input pin selection

UART1 RxD1 can be chosen by software to be input to one of the two pins set

13.2 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer

data format.

Table 13.3 lists the specifications of UART mode. Figure 13.11 shows the UARTi transmit/receive mode register.

Transfer data format

Transfer clock

Transmission start

condition

Reception start condi-

tion

Interrupt request gen-

eration timing

Error detection

Select function

Table 13.3 Specifications of UART Mode

Note 1: "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator.

Note 2: fEXT is input from the CLKi pin.

Note 3: If an overrun error occurs, the UARTi receive buffer will be indeterminate. Note also that the UARTi

receive interrupt request bit does not change.

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