TMP93CS44 datasheet(113/224 Pages) TOSHIBA

113 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-111

TREG4 timer register is of double buffer structure, which is paired with register

buffer. The timer control register T45CR<DB4EN> controls whether the double buffer

structure should be enabled or disabled. Disabled when <DB4EN>

= 0, while enabled

when <DB4EN>

= 1.

When the double buffer is enabled, the timing to transfer data from the register

buffer to the timer register is at the match between the up counter (UC4) and timer

After reset, TREG4 and TREG5 are undefined. To use the 16-bit timer after reset,

data should be written beforehand.

When reset, it will be initialized to <DB4EN>

= 0, whereby the double buffer is

disabled. To use the double buffer, write data in the timer register, set <DB4EN>

= 1,

and then write the following data in the register buffer.

TREG4 and register buffer are allocated to the same memory addresses

000030H/000031H. When <DB4EN>

= 0, same value will be written in both the timer

= 1, the value is written into only the

4. Capture register

These 16-bit registers are used to latch the values of the up counter.

Data in the capture registers should be read all 16 bits. For example, using a 2-byte

data load instruction or two 1-byte data load instruction, from the lower 8-bit followed

by the upper 8 bits.

CAP1 to CAP4 are read-only registers, so it cannot be written by software.

Upper 8 bits

(CAP1H)

Lower 8 bits

(CAP1L)

000035H

000034H

CAP1

Upper 8 bits

(CAP2H)

Lower 8 bits

(CAP2L)

000037H

000036H

CAP2

Timer 4

Upper 8 bits

(CAP3H)

Lower 8 bits

(CAP3L)

000045H

000044H

CAP3

Upper 8 bits

(CAP4H)

Lower 8 bits

(CAP4L)

000047H

000046H

CAP4

Timer 5

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