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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS44 датащи(PDF) 117 Page - Toshiba Semiconductor |
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TMP93CS44 датащи(HTML) 117 Page - Toshiba Semiconductor |
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117 / 224 page  TMP93CS44/S45 2004-02-10 93CS44-115 Shows the block diagram of this mode. Figure 3.8.12 Block Diagram of 16-Bit PPG Mode In 16-bit PPG mode, set the registers is the following order: 7 6 5 4 3 2 1 0 T45CR ← 0 X X X X X − 0 Double buffer of TRG4 disable. TRUN ← − X − 0 − − − − Stop timer 4. TREG4 ← * * * * * * * * Set the duty (16 bits). TREG5 ← * * * * * * * * Set the cycle (16 bits). T45CR ← 0 X X X X X − 1 Double buffer of TREG4 enable. (Change the duty and cycle at the interrupt INTTR5.) T4FFCR ← X X 0 0 1 1 1 0 Set the mode to invert TFF4 at the match with TREG4/TREG5, and also set the TFF4 to “0”. T4MOD ← 0 0 1 0 0 1 ** (** = 01, 10, 11) Select the internal clock for the input, and disable the capture function. P4CR ← − − − 1 − − − − P4FC ← − X X 1 X X − X Assign P44 as TO4. TRUN ← 1 X − 1 − − − − Start timer 4. X: Don’t care, −: No change Selector 16-bit up counter UC4 16-bit comparator 16-bit comparator TI4 pin φT1 φT4 φT16 F/F (TFF4) TREG4 Register buffer 4 TREG5 Selector T45CR<DB4EN> TREG4-WR TRUN<T4RUN> TO4 (PPG output) Internal data bus Clear Match |
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