TMP93CS44 datasheet(112/224 Pages) TOSHIBA

112 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-110

The clock selected among fFPH clock, fc/16 clock, and fs clock is divided by 4 and

input to this prescaler. This is selected by prescaler clock selection register

SYSCR0<PRCK1:0>.

Resetting sets <PRCK1:0> to 00, therefore fFPH/4 clock is input.

The 16-bit timer 4, 5 selects between 3 clock inputs:

φT1, φT4, and φT16 among the

prescaler outputs.

This prescaler can be run or stopped by the timer operation control register

TRUN<PRRUN>. Counting starts when <PRRUN> is set to 1, while the prescaler is

cleared to 0 and stops operation when <PRRUN> is set to 0.

When the IDLE1 mode (Operates only oscillator) is used, set TRUN<PRRUN> to 0 to

stop this prescaler before “HALT” instruction is executed.

2. Up counter

UC4 is a 16-bit binary counter which counts up according to the input clock specified

by T4MOD<T4CLK1:0> register.

As the input clock, one of the internal clocks

φT1, φT4, and φT16 from 9-bit prescaler

(also used for 8-bit timer), and external clock from TI4 pin (also used as P42/INT4 pin)

can be selected. When reset, it will be initialized to <T4CLK1:0>

= 00 to select TI4

input mode. Counting or stop and clear of the counter is controlled by timer operation

control register TRUN<T4RUN>.

When clearing is enabled, up counter UC4 will be cleared to 0 each time it coincides

matches the timer register TREG5. The “clear enable/disable” is set by T4MOD<CLE>.

If clearing is disabled, the counter operates as a free-running counter.

A timer overflow interrupt (INTTO4) is generated when UC4 overflow occurs.

3. Timer registers

These two 16-bit registers are used to set the interval time. When the value of up

counter UC4 matches the set value of this timer register, the comparator match detect

signal will be active.

Setting data for both upper and lower timer registers (TREG4 and TREG5) is always

needed. For example, either using 2-byte data transfer instruction or using 1-byte data

transfer instruction twice for lower 8 bits and upper 8 bits in order.

TREG4 to TREG7 are write-only registers, so they can not be read by software.

Upper 8 bits

(TREG4H)

Lower 8 bits

(TREG4L)

000031H

000030H

TREG4

Upper 8 bits

(TREG5H)

Lower 8 bits

(TREG5L)

000033H

000032H

TREG5

Timer 4

Upper 8 bits

(TREG6H)

Lower 8 bits

(TREG6L)

000041H

000040H

TREG6

Upper 8 bits

(TREG7H)

Lower 8 bits

(TREG7L)

000043H

000042H

TREG7

Timer 5

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