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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS41 датащи(PDF) 150 Page - Toshiba Semiconductor |
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TMP93CS41 датащи(HTML) 150 Page - Toshiba Semiconductor |
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150 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-148 1. One-shot pulse output from external trigger pulse To program this application, set the up counter UC4 in free-running mode with the internal input clock, input the external trigger pulse from the TI4 pin, and load the value of the up counter into capture register CAP1 at the rising edge of the TI4 pin. Then set T4MOD<CAP12M1:0> = 01. When the interrupt INT4 is generated at the rising edge of the TI4 input, set the CAP1 value (c) plus a delay time (d) to TREG4 ( = c + d), and set the above set value (c + d) plus a one-shot pulse width (p) to TREG5 ( = c + d + p). When the interrupt INT4 occurs, the T4FFCR<EQ5T4 and EQ4T4>register should be set so that the TFF4 inversion is enabled only when the up counter value matches TREG4 or TREG5. When interrupt INTTR5 occurs, this inversion will be disabled. Figure 3.9.15 One-shot Pulse Output (with delay) c + d Counter clock (Internal clock) TI4 pin input (External trigger pulse) Match with TREG4 Match with TREG5 Timer output pin TO4 Load the up counter value into capture register 1 (CAP1) when INT4 occurs c + d + p Set the counter in free-running mode. INTTR5 occurrence Enable inversion Disable inversion caused by loading of the up counter value into CAP1. Enable inversion Delay time Pulse width (d) (p) c |
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