TMP93CS41 datasheet(146/248 Pages) TOSHIBA

146 / 248 page

TMP93CS40/TMP93CS41

2004-02-10

93CS40-144

5. Capture input control

This circuit controls the timing of latching the value of up counter UC4 into CAP1 and

CAP2. The latch timing of the capture register is controlled by register

T4MOD<CAP12M1:0>. There are four possible settings:

•

When T4MOD<CAP12M1:0>

= 00

Capture function is disabled. Disable is the default on resetting.

•

When T4MOD<CAP12M1:0>

= 01

Data are loaded to CAP1 at the rising edge of the TI4 pin (which is also used as P80

or INT4) input, while data are loaded to CAP2 at the rising edge of the TI5 pin (also

used as P81 or INT5) input. (Time difference measurement.)

•

When T4MOD<CAP12M1:0>

= 10

Data are loaded to CAP1 at the rising edge of the TI4 pin input, and to CAP2 at the

falling edge. Only in this setting, interrupt INT4 occurs at the falling edge. This results

in pulse width measurement.

•

When T4MOD<CAP12M1:0>

= 11

Data are loaded to CAP1 at the rising edge of timer flip-flop TFF1, and to CAP2 at

the falling edge.

Besides, the value of the up counter can be loaded to capture registers by software.

Whenever “0” is written in T4MOD<CAP1IN>, the current value of the up counter will

be loaded to capture register CAP1. It is necessary to keep the prescaler in RUN mode

(TRUN<PRRUN> has to be 1).

6. Comparator

There are 16-bit comparators which compare the up counter UC4 value with the values

set in TREG4 and TREG5 to detect matches. When a match is detected, these comparators

generate interrupts INTTR4 or INTTR5 respectively. The up counter UC4 is cleared only

when UC4 matches TREG5. The clearing of up counter UC4 can be disabled by setting

T4MOD<CLE>

= 0.

7. Timer flip-flop (TFF4)

This flip-flop is inverted by the match detect signal from the comparators or the latch

signals to the capture registers. Disable or enable of inversion can be set for each element

by T4FFCR<CAP2T4, CAP1T4, EQ5T4 and EQ4T4>. TFF4 will be inverted when “00” is

written in T4FFCR<TFF4C1:0>. Also it is set to “1” when “01” is written, and cleared when

“10”S is written. The value of TFF4 can be output to the timer output pin TO4 (which is also

used as P82). TFF4 is undefined on resetting.

8. Timer flip-flop (TFF5)

This flip-flop is inverted when the comparator detects that the up counter signal (UC4)

and the contents of the timer register TREG5 match, or when the contents of the up counter

are latched to the capture register CAP2. Disable or enable of inversion can be set for each

element by T4MOD<CAP2T5 and EQ575>. TFF5 will be inverted when “00” is written in

T4FFCR<TFF5C1:0>. Also it is set to “1” when “01” is written, and cleared when “10” is

written. The value of TFF5 can be output to the timer output pin TO5 (also used as P83).

TFF5 is undefined on resetting.

Note:

This flip-flop (TFF5) is contained only in the 16-bit timer 4.

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