AD9927BBCZ datasheet(24/100 Pages) AD

24 / 100 page

AD9927

Rev. 0 | Page 24 of 100

Length

Range

Description

HBLKALT_PAT1

0 to 5 even repeat area

HBLK Mode 2, Odd Field Repeat Area 0 pattern, selected from even field

repeat areas previously defined.

HBLKALT_PAT2

0 to 5 even repeat area

HBLK Mode 2, Odd Field Repeat Area 1 pattern.

HBLKALT_PAT3

0 to 5 even repeat area

HBLK Mode 2, Odd Field Repeat Area 2 pattern.

HBLKALT_PAT4

0 to 5 even repeat area

HBLK Mode 2, Odd Field Repeat Area 3 pattern.

HBLKALT_PAT5

0 to 5 even repeat area

HBLK Mode 2, Odd Field Repeat Area 4 pattern.

HBLKALT_PAT6

0 to 5 even repeat area

HBLK Mode 2, Odd Field Repeat Area 5 pattern.

HBLK

H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS

H1/H3

H2/H4

HBLKSTART

HBLKTOGE1

HBLKTOGE2

HBLKEND

HBLKTOGE3

HBLKTOGE4

HBLKLEN

HBLKREP NUMBER 1

HBLKREP NUMBER 2

HBLKREP NUMBER 3

HBLKREP = 3

Figure 28. HBLK Repeating Pattern Using HBLKMODE = 1

HBLK Mode 1 Operation

Multiple repeats of the HBLK signal are enabled by setting

HBLKMODE to 1. In this mode, the HBLK pattern can be

generated using a different set of registers: HBLKSTART,

HBLKEND, HBLKLEN, and HBLKREP, along with the six

toggle positions (see Figure 28).

Separate toggle positions are available for even and odd lines. If

alternation is not needed, the same values should be loaded into

the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.

Generating HBLK Line Alternation

HBLK Mode 0 and HBLK Mode 1 provide the ability to

alternate different HBLK toggle positions on even and odd

lines. HBLK line alternation can be used in conjunction with

V-pattern odd/even alternation or on its own. Separate toggle

positions are available for even and odd lines. If even/odd line

alternation is not required, the same values should be loaded into

the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.

Increasing H-Clock Width During HBLK

HBLK Mode 0 and HBLK Mode 1 allow the H1 to H8 pulse

width to be increased during the HBLK interval. As shown in

Figure 29, the H-clock frequency can be reduced by a factor of

1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30. To enable

this feature, the HCLK_WIDTH register (Address 0x34,

Bits [7:4]) is set to a value between 1 and 15. When this register

is set to 0, the wide HCLK feature is disabled. The reduced

frequency occurs only for H1 to H8 pulses that are located

within the HBLK area.

The HCLK_WIDTH register is generally used in conjunction

with special HBLK patterns to generate vertical and horizontal

mixing in the CCD.

Note that the wide HCLK feature is available only in HBLK

Mode 0 and HBLK Mode 1. HBLK Mode 2 does not support

wide HCLKs.

Table 12. HCLK Width Register

Length

Description

HCLK_WIDTH

Controls H1 to H8 width during

HBLK as a fraction of pixel rate

0: same frequency as pixel rate

1: 1/2 pixel frequency, that is,

doubles the HCLK pulse width

2: 1/4 pixel frequency

3: 1/6 pixel frequency

4: 1/8 pixel frequency

5: 1/10 pixel frequency

…

15: 1/30 pixel frequency

AD9927BBCZ датащи(PDF) 24 Page - Analog Devices

AD9927BBCZ датащи(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

датащи скачать

ссылки URL