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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9927BBCZ датащи(PDF) 87 Page - Analog Devices |
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AD9927BBCZ датащи(HTML) 87 Page - Analog Devices |
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87 / 100 page  AD9927 Rev. 0 | Page 87 of 100 Address Data Bits Default Value Update Type Name Description 24 [0] 0 SCK SEL_VCO 1: internal CP clock select VCO. [1] 1 SEL_DIV 1: internal CP clock select divided-down version of CLI (default). [2] 0 SEL_CLI 1: internal CP clock select CLI. [3] 0 O31V 1: CP output voltage is 3.1 V. [4] 0 O32V 1: CP output voltage is 3.2 V. [5] 1 O33V 1: CP output voltage is 3.3 V. [6] 0 O34V 1: CP output voltage is 3.4 V. [7] 1 TEST Test use only. Use default values only. [8] 1 TEST Test use only. Use default values only. [9] 1 TEST Test use only. Use default values only. [10] 1 TEST Test use only. Use default values only. [11] 0 TEST Test use only. Use default values only. [12] 0 TEST Test use only. Use default values only. [13] 0 TEST Test use only. Use default values only. [14] 1 CP_PDN Charge pump power-down. 1: power-down; 0: CP is running. 25 [24:0] 0 SCK VT_STBY12 [23:0] Standby1 and Standby2 polarity for XV[23:0]. [24] Standby1 and Standby2 polarity for XSUBCK. Settings also apply when OUTCONTROL = low. 26 [24:0] 0 SCK VT_STBY3 [23:0] Standby3 polarity for XV [23:0]. [24] Standby3 polarity for XSUBCK. 27 [7:0] 0 SCK GP_STDBY12 Standby1 and Standby2 polarity for GPO [7:0]. Settings also apply when OUTCONTROL = low. [15:8] GP_STDBY3 Standby3 polarity for GPO [7:0]. Table 52. Memory Configuration and MODE Registers Address Data Bits Default Value Update Type Name Description 28 [4:0] 0 SCK VPATNUM Total number of V-pattern groups. [9:5] 0 SEQNUM Total number of V-sequences. 2A [2:0] 0 SCK MODE Total number of fields in MODE. 2B [4:0] 0 SCK FIELD0 Selected first field in MODE. [9:5] 0 FIELD1 Selected second field in MODE. [14:10] 0 FIELD2 Selected third field in MODE. [19:15] 0 FIELD3 Selected fourth field in MODE. [24:20] 0 FIELD4 Selected fifth field in MODE. 2C [4:0] 0 SCK FIELD5 Selected sixth field in MODE. [9:5] 0 FIELD6 Selected seventh field in MODE. Table 53. Timing Core Registers Address Data Bits Default Value Update Type Name Description 30 [5:0] 0 SCK H1POSLOC H1 rising edge location. [13:8] 20 H1NEGLOC H1 falling edge location. [16] 1 H1POL H1 polarity control. 0: inverse of Figure 20; 1: no inversion. 31 [5:0] 0 SCK H2POSLOC H2 rising edge location (H5 in HCLK Mode 3). [13:8] 20 H2NEGLOC H2 falling edge location (H5 in HCLK Mode 3). [16] 1 H2POL H2 polarity (H5 in HCLK Mode 3). 0: inverse of Figure 20; 1: no inversion. 32 [5:0] 0 SCK HLPOSLOC HL rising edge location. [13:8] 20 HLNEGLOC HL falling edge location. [16] 1 HLPOL HL polarity control. 0: inverse of Figure 20; 1: no inversion. |
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