AD9927BBCZ datasheet(85/100 Pages) AD

85 / 100 page

AD9927

Rev. 0 | Page 85 of 100

COMPLETE REGISTER LISTING

When an address contains less than 28 data bits, all remaining bits must be written as 0s.

Table 48. AFE Registers

Address

Data

Bits

Default

Value

Update

Type

Name

Description

[1:0]

SCK

STANDBY

Standby modes. 0: normal operation; 1: Standby1 mode;

2: Standby2 mode; 3: Standby3 mode.

[2]

CLPENABLE

0: disable OB clamp; 1: enable OB clamp.

[3]

CLPSPEED

0: select normal OB clamp settling; 1: select fast OB clamp settling.

[4]

FASTUPDATE

0: ignore CDS gain; 1: very fast clamping when CDS gain is updated.

[5]

PBLK_LVL

0: blank data outputs to 0 during PBLK;

1: blank data outputs to programmed clamp level during PBLK.

[6]

DCBYP

0: enable input dc restore circuit during PBLK;

1: disable input dc restore circuit during PBLK.

[0]

SCK

DOUTDISABLE

0: data outputs are driven; 1: data outputs are three-stated.

[1]

DOUTLATCH

0: latch data outputs using the rising edge of DOUTPHASEP

(DOUTPHASEP register setting);

1: output latch is transparent.

[2]

GRAY_EN

1: enable gray encoding of the digital data outputs.

[3]

TEST

Set to 0.

[0]

SCK

TEST

Do not access, or set to 0.

[23:0]

FFFFFF

SCK

TEST

Do not access, or set to 0xFFFFFF.

[2:0]

CDSGAIN

CDS gain setting. 0: −3 dB; 4: 0 dB; 6: +3 dB; 7: +6 dB.

All other values are invalid.

[9:0]

VGAGAIN

VGA gain, 6 dB to 42 dB (0.035 dB per step).

[9:0]

1EC

CLAMPLEVEL

Optical black clamp level, 0 to 1023 LSB (1 LSB per step).

[0]

CLIDIVIDE

0: no division of CLI; 1: divide CLI input frequency by 2.

Table 49. Miscellaneous Registers

Address

Data

Bits

Default

Value

Update

Type

Name

Description

[0]

SCK

SW_RST

Software reset. Bit self-clears to 0 when a reset occurs.

1: reset Address 0x00 to Address 0xFF to default values.

[0]

OUTCONTROL

0: make all outputs dc inactive; 1: enable outputs at next VD

edge.

[0]

SCK

RSTB_EN

1: configure SYNC pin as RSTB input signal.

[4:1]

TEST

Test mode only. Must be set to 0.

[0]

SCK

SYNCENABLE

1: external synchronization enable (configures Pin D3 as an

input).

[1]

SYNCPOL

SYNC active polarity.

[2]

SYNCSUSPEND

Suspend clocks during SYNC active pulse. 0: don’t suspend;

1: suspend.

[3]

ENH_SYNC_EN

1: enable enhanced sync/shutter operations.

[4]

SYNC_MASK_HD

1: mask HD during SYNCSUSPEND.

[5]

SYNC_MASK_VD

1: mask VD during SYNCSUSPEND.

[6]

SYNC_MASK_V

1: mask XV outputs during SYNCSUSPEND.

[7]

SHADOW_EN

1: enable use of shadow registers.

[12:8]

TEST

Test mode only. Must be set to 0.

[13]

UPDATE_SHADOW

1: writes to shadow bits affect shadow registers, not primary.

[14]

SWSYNC

1: initiate software SYNC event (self-clears to 0 after SYNC).

[0]

SCK

TGCORE_RSTB

Timing core reset bar. 0: reset TG core; 1: resume operation.

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