AD9927BBCZ datasheet(86/100 Pages) AD

86 / 100 page

AD9927

Rev. 0 | Page 86 of 100

Address

Data

Bits

Default

Value

Update

Type

Name

Description

[0]

SCK

OSC_RSTB

CLO oscillator reset bar.

0: oscillator in power-down state; 1: resume oscillator

operation.

[27:0]

SCK

TEST

Test mode only. Must be set to 0.

[12:0]

SCK

UPDATE

Serial update line.

Sets the line (HD) within the field to update the VD-updated

registers.

[13]

PREVENTUP

Prevents the update of the VD-updated registers.

0: normal update; 1: prevent update of VD-updated registers.

[14]

SYNC_RST_SHUTEN

1: enable reset of the shutter control after SYNC operation

occurs.

[15]

REG_RST_SHUT

1: forces shutter control to reset.

[16]

GPO_RST_SYNC

1: reset shutter and GPO control at SYNC operation.

[27:0]

SCK

TEST

Test mode only. Must be set to 0.

[27:0]

SCK

TEST

Test mode only. Must be set to 0.

[27:0]

SCK

TEST

Test mode only. Must be set to 0.

[27:0]

SCK

TEST

Test mode only. Must be set to 0xA.

[23:0]

FF0000

SCK

VSGSELECT

Each bit selects XV pulses for use as VSG pulses.

[23:0]

SCK

VSGMASK_CTL

VSG masking. Overrides settings in field registers when

enabled.

[24]

VSGMASK_CTL_EN

0: disable VSGMAK_CTL bits. VSG masking is controlled by field

registers.

1: enable VSGMASK_CTL bits to control VSG masking

[0]

SCK

HCNT14_EN

1: enable 14-bit H-counter.

[1]

PBLK_MASK_EN

1: disable clamp operation if PBLK is active at the same time as

CLPOB.

Table 50. VD/HD Registers

Address

Data Bits

Default Value

Update Type

Name

Description

[0]

SCK

MASTER

VD/HD master or slave mode. 0: slave mode; 1: master mode.

[0]

VDHDPOL

VD/HD active polarity. 0 = low, 1 = high.

[12:0]

HDRISE

Rising edge location for HD. Minimum value is 36 pixels.

[25:13]

VDRISE

Rising edge location for VD.

Table 51. I/O and Charge Pump Registers

Address

Data

Bits

Default

Value

Update

Type

Name

Description

[0]

SCK

OSC_NVR

Oscillator normal voltage range. Set to match CLIVDD supply voltage.

0 = 1.8 V, 1 = 3.3 V

[1]

XV_NVR

XV output normal voltage range. Set to match XVVDD supply voltage.

0 = 1.8 V, 1 = 3.3 V

[2]

IO_NVR

I/O normal voltage range. Set the match IOVDD supply voltage.

0 = 1.8 V, 1 = 3.3 V

[3]

DATA_NVR

Data pin normal voltage range. Set to match DRVDD supply voltage.

0 = 1.8 V I/O, 1 = 3.3 V I/O.

[4]

TEST

Test use only. Set to 0.

[5]

TEST

Test use only. Set to 0.

[6]

LDO_32_EN

1: internal regulator enable for 3.2 V output.

[9:7]

HCLKMODE

Selects HCLK output configuration. Should be written to desired value.

001 = Mode 1, 010 = Mode 2, 100 = Mode 3. All other values are invalid.

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