AD9927BBCZ datasheet(66/100 Pages) AD

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AD9927

Rev. 0 | Page 66 of 100

MANUAL SHUTTER OPERATION USING

ENHANCED SYNC MODES

The AD9927 also supports an external signal to control exposure,

using the SYNC input. Generally, the SYNC input is used as an

asynchronous reset signal during master mode operation. When

the enhanced SYNC mode is enabled, the SYNC input provides

additional control of the exposure operation.

Normal SYNC Mode (Mode 1)

By default, the SYNC input is used in master mode for

synchronizing the internal counters of the AD9927 with

external timing. The SYNC During Master Mode Operation

section describes how horizontal, vertical, and field designator

signals are reset by the rising edge of the SYNC pulse. Figure 79

also shows how this mode operates, highlighting the behavior of

the mode field designator.

Enhanced SYNC Modes (Modes 2 and 3)

The enhanced SYNC modes can be used to accommodate

unique synchronization requirements during exposure

operations. In SYNC Mode 2, the V and VSG outputs are

suspended and the VD output is masked. The V-outputs are

held at the dc value established by the Sequence 0 start polarities.

There is no SCP operation, but the H-counter is still enabled.

Finally, the AFE sampling clocks, HD, H/RG, CLPOB, HBLK,

are operational and use Sequence 0 behavior. See Figure 80 for

more details.

To enable the enhanced SYNC modes, set the register

ENH_SYNC_EN (Address 0x13 Bit [3]) to 1.

Mode 3 uses all of these features, but the V-outputs are continuous

through the SYNC pulse interval. VD control pulses are masked

during the SYNC interval, and the HD pulse can also be masked,

if required (see Figure 81).

It is important to note that in both of these enhanced modes,

the SYNC pulse resets the counters at both the falling edge and

the rising edge of the SYNC pulse.

When using special SYNC Mode 2 or 3, the VD-updated

registers, such as PRIMARY_ACTION, are not updated during

the SYNC interval, and the SCP0 function is ignored and held

at 0 (see Figure 82).

When using either SYNC Mode 2 or 3, both the rising and falling

edges increment the internal field designator; therefore, the new

SEQ0 data. However, this does not occur if the MODE register is

to create an output of one field. In that case, the region, sequence,

and group information does not change (see Figure 83).

Shutter Operation in SLR Mode

Referring to Figure 84,

To turn on VSUB, write to the appropriate GP registers to

trigger VSUB and start the manual exposure

[PRIMARY_ACTION = 5]. This change takes effect after

the next VD, and SUBCK is suppressed during the

exposure and readout phases.

To turn on MSHUT during the interval between the next

VD and SYNC, write to the appropriate GP register. When

MSHUT is in the on position, it has line and pixel control.

This change takes effect on the SYNC falling edge since

there is an internal VD.

If the MODE register is programmed to cycle through

multiple fields (5, 7, 3, 5, 7, 3, …, in this example), the internal

field designator increments. If the MODE register is not

required to increment, set up the MODE register such that it

outputs only one field. This prevents the MODE counter

from incrementing during the SYNC interval.

Write to the manual readout trigger to begin the manual

readout [PRIMARY_ACTION = 6]. Write to the

appropriate GP registers to trigger MSHUT to toggle low at

the end of the exposure. This change takes effect on the

SYNC rising edge during readout. Since VD register

update is disabled, the trigger takes effect on the SYNC

rising edge. The MSHUT falling edge is aligned to the

SYNC rising edge. Because the MSHUT falling edge is

aligned with VD, it may be necessary to insert a dummy

VD to delay the readout.

Note that since the internal exposure counter (PRIMARY

counter) is not used during manual SYNC mode operation and

the VD register update is disabled, control is lost on the fine

placement of the GP signals for VSUB, MSHUT, and STROBE

edges while SYNC is low.

New Serial Registers

SYNC Modes 2 and 3 are controlled using the registers listed

in Table 44.

Table 44. Registers for Enhanced SYNC Modes

Length

Description

ENH_SYNC_EN

HI active to enable

(default LO)

SYNC_MASK_V

HI active to enable masking

(default LO)

SYNC_MASK_VD

HI active to enable masking

(default HI)

SYNC_MASK_HD

HI active to enable masking

(default HI)

Note that registers for enhanced SYNC modes are located at

Address 0x13 Bits [6:3].

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