AD9927BBCZ datasheet(44/100 Pages) AD

44 / 100 page

AD9927

Rev. 0 | Page 44 of 100

Vertical Sensor Gate (Shift Gate) Patterns

In an interline CCD, the vertical sensor gate (VSG) pulses are

used to transfer the pixel charges from the light-sensitive image

area into light-shielded vertical registers. From the light-

shielded vertical registers, the image is clocked out line-by-line

using the vertical transfer pulses (XV signals) in conjunction

with the high speed horizontal clocks. The AD9927 has 24

vertical signals, and each signal can be assigned as a VSG pulse

instead of an XV pulse.

Table 19 summarizes the VSG control registers, which are

mostly located in the field registers space (see Table 17). The

VSGSELECT register (Address 0x1C in the fixed address space)

determines which vertical outputs are assigned as VSG pulses.

When a signal is selected to be a VSG pulse, only the starting

polarity and two of the V-pattern toggle positions are used. The

VSGPATSEL register in the sequence registers is used to assign

either TOG1 and TOG2 or TOG3 and TOG4 to the VSG signal.

Note that only two of the four V-pattern toggle positions are

available when a vertical signal is selected to be a VSG pulse.

The SGACTLINE1 and SGACTLINE2 registers are used to

select which line in the field is the VSG line. The VSG active

line location is used to reference when the substrate clocking

(SUBCK) signal begins to operate in each field. For more

information, see the Substrate Clock Operation (SUBCK)

section.

Also located in the field registers, the SGMASK register selects

which individual VSG pulses are active in a given field. Therefore,

all SG patterns to be preprogrammed into the V-pattern registers

and the appropriate pulses for the different fields can be enabled

separately.

The AD9927 is an integrated AFETG + V-driver, so the

connections between the AFETG and V-driver are fixed, as

shown in Figure 53. The VSGSELECT must be programmed to

0xFF8000.

Table 19. VSG Control Registers (also see Field Registers in Table 17)

Length

Range

Description

24b

High/low

Selection of VSG signals from XV signals. Set to 1 to make signal a VSG.

[0]: XV1 selection (0 = XV pulse; 1 = VSG pulse).

VSGSELECT

(Located in Fixed

Address Space, 0x1C)

[1]: XV2 selection.

…

[23]: XV24 selection.

VSGPATSEL

24b

High/low

When VSG signal is selected using the VSGSELECT register, VSGPATSEL

selects which V-pattern toggle positions are used. When set to 0, Toggle 1

and Toggle 2 are used. When set to 1, Toggle 3 and Toggle 4 are used.

[0]: XV1 selection (0 = use TOG1, TOG2; 1 = use TOG3, TOG4).

[1]: XV2 selection.

…

[23]: XV24 selection.

SGMASK

24b

High/low, each VSG

Set high to mask each individual VSG output.

[0]: XV1 mask.

…

[23]: XV24 mask.

SGACTLINE1

13b

0 to 8191 line no.

Selects the line in the field where the VSG signals are active.

SGACTLINE2

13b

0 to 8191 line no.

Selects a second line in the field to repeat the VSG signals. If not used,

set this equal to SGACTLINE1 or to the maximum value.

VSG PATTERN

PROGRAMMABLE SETTINGS FOR EACH PATTERN:

1START POLARITY OF PULSE (FROM VPOL IN SEQUENCE REGISTERS).

2FIRST TOGGLE POSITION (FROM V-PATTERN REGISTERS).

3SECOND TOGGLE POSITION (FROM V-PATTERN REGISTERS).

4ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (FROM FIELD REGISTERS).

Figure 52. Vertical Sensor Gate Pulse Placement

AD9927BBCZ датащи(PDF) 44 Page - Analog Devices

AD9927BBCZ датащи(HTML) 44 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

датащи скачать

ссылки URL