AD9927BBCZ datasheet(88/100 Pages) AD

88 / 100 page

AD9927

Rev. 0 | Page 88 of 100

Address

Data

Bits

Default

Value

Update

Type

Name

Description

[5:0]

SCK

RGPOSLOC

RG rising edge location.

[13:8]

RGNEGLOC

RG falling edge location.

[16]

RGH2POL

RG polarity control. 0: inverse of Figure 20, 1: no inversion.

[0]

SCK

H1HBLKRETIME

Retime H1, H2, HL HBLK to the internal clock. 0: no retime; 1: retime.

[1]

H2HBLKRETIME

Recommended setting is retime enabled (1). Setting to 1 adds one cycle delay

to programmed HBLK positions.

[2]

HLHBLKRETIME

[3]

HL_HBLK_EN

Enable HBLK for HL output. 0: disable; 1: enable.

[7:4]

HCLK_WIDTH

Enables wide H-clocks during HBLK interval. Set to 0 to disable.

[2:0]

SCK

H1DRV

H1 drive strength. 0: off; 1: 4.3 mA; 2: 8.6 mA; 3: 12.9 mA; 4: 4.3 mA;

5: 8.6 mA; 6: 12.9 mA; 7: 17.2 mA.

[6:4]

H2DRV

H2 drive strength (same range as H1DRV).

[10:8]

H3DRV

H3 drive strength (same range as H1DRV).

[14:12]

H4DRV

H4 drive strength (same range as H1DRV).

[18:16]

HLDRV

HL drive strength (same range as H1DRV).

[22:20]

RGDRV

RG drive strength (same range as H1DRV).

[2:0]

SCK

H5DRV

H5 drive strength (same range as H1DRV).

[6:4]

H6DRV

H6 drive strength (same range as H1DRV).

[10:8]

H7DRV

H7 drive strength (same range as H1DRV).

[14:12]

H8DRV

H8 drive strength (same range as H1DRV).

[5:0]

SCK

SHDLOC

SHD sampling edge location.

[11:6]

SHPLOC

SHP sampling edge location.

[17:12]

SHPWIDTH

SHP width (controls input dc restore switch active time).

[5:0]

SCK

DOUTPHASEP

DOUT phase control, positive edge. Specifies location of DOUT.

[11:6]

DOUTPHASEN

DOUT phase control, negative edge. Always set to DOUTPHASEP plus

32 edges to maintain 50% duty cycle of internal DOUTPHASE clocking.

[12]

DCLKMODE

DCLK mode. 0: DCLK tracks DOUT; 1: DCLK phase is fixed.

[14:13]

DOUTDELAY

Data output delay (tOD) with respect to DCLK rising edge.

0: no delay; 1: ~3 ns; 2: ~6 ns; 3: ~9 ns

[15]

DCLKINV

Invert DCLK output. 0: no inversion, 1: inversion of DCLK.

[2:0]

SCK

CPHMASK

Enable H-masking during CP operation.

Table 54. Test Registers—Do Not Access

Address

Data Bits

Default Value

Update

Name

Description

3E ~ 4F

Test registers only. Do not access.

Table 55. Test Registers—Do Not Access

Address

Data Bits

Default Value

Update Type

Name

Description

50 ~ 6F

Test registers only. Do not access.

Table 56. Shutter and GPO Registers

Address

Data

Bits

Default

Value

Update

Type

Name

Description

[2:0]

PRIMARY_ACTION

Selects action for primary and secondary counters.

[5:3]

SECOND_ACTION

0: idle (do nothing) autoreset on VD.

1: activate counter (primary: auto exposure/readout).

2: RapidShot: wrap/repeat counter.

3: ShotTimer: delay start of count.

4: ShotTimer with RapidShot.

5: SLR exposure (manual).

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