AD9927BBCZ datasheet(20/100 Pages) AD

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AD9927

Rev. 0 | Page 20 of 100

HORIZONTAL CLAMPING AND BLANKING

The AD9927’s horizontal clamping and blanking pulses are fully

programmable to suit a variety of applications. Individual

control is provided for CLPOB, PBLK, and HBLK in the

different regions of each field. This allows the dark pixel

clamping and blanking patterns to be changed at each stage of

the readout in order to accommodate different image transfer

timing and high speed line shifts.

Individual CLPOB and PBLK Patterns

The AFE horizontal timing consists of CLPOB and PBLK, as

shown in Figure 23. These two signals are programmed

independently using the registers in Table 10. The start polarity

for the CLPOB (and PBLK) signal is CLPOBPOL (PBLKPOL),

and the first and second toggle positions of the pulse are

CLPOBTOG1 (PBLKTOG1) and CLPOBTOG2 (PBLKTOG2).

Both signals are active low and should be programmed

accordingly.

A separate pattern for CLPOB and PBLK can be programmed

for each vertical sequence. As described in the Vertical Timing

Generation section, several V-sequences can be created, each

containing a unique pulse pattern for CLPOB and PBLK. Figure 49

shows how the sequence change positions divide the readout field

into different regions. By assigning a different V-sequence to

each region, the CLPOB and PBLK signals can change with

each change in the vertical timing.

CLPOB and PBLK Masking Areas

Additionally, the AD9927 allows the CLPOB and PBLK signals to

be disabled in certain lines in the field without changing any of

the existing CLPOB pattern settings.

To use CLPOB (or PBLK) masking, the CLPMASKSTART

(PBLKMASKSTART) and CLPMASKEND (PBLKMASKEND)

registers are programmed to specify the start and end lines in

the field where the CLPOB (PBLK) patterns are ignored. The

three sets of start and end registers allow up to three CLPOB

(PBLK) masking areas to be created.

The CLPOB and PBLK masking registers are not specific to a

certain V-sequence; they are always active for any existing field

of timing. During operation, to disable the CLPOB masking

feature, these registers must be set to the maximum value of

0x1FFF or a value greater than the programmed VD length.

Note that to disable CLPOB (and PBLK) masking during power-up,

it is recommended to set CLPMASKSTART (PBLKMASKSTART)

to 8191 and CLPMASKEND (PBLKMASKEND) to 0. This

prevents any accidental masking caused by register update events.

Table 10. CLPOB and PBLK Pattern Registers

Length

Range

Description

CLPOBPOL

High/low

Starting polarity of CLPOB for each V-sequence.

PBLKPOL

High/low

Starting polarity of PBLK for each V-sequence.

CLPOBTOG1

13b

0 to 8191 pixel location

First CLPOB toggle position within line for each V-sequence.

CLPOBTOG2

13b

0 to 8191 pixel location

Second CLPOB toggle position within line for each V-sequence.

PBLKTOG1

13b

0 to 8191 pixel location

First PBLK toggle position within line for each V-sequence.

PBLKBTOG2

13b

0 to 8191 pixel location

Second PBLK toggle position within line for each V-sequence.

CLPMASKSTART

13b

0 to 8191 line location

CLPOB masking area—starting line within field (maximum of three areas).

CLPMASKEND

13b

0 to 8191 line location

CLPOB masking area—ending line within field (maximum of three areas).

PBLKMASKSTART

13b

0 to 8191 line location

PBLK masking area—starting line within field (maximum of three areas).

PBLKMASKEND

13b

0 to 8191 line location

PBLK masking area—ending line within field (maximum of three areas).

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