AD9927BBCZ datasheet(18/100 Pages) AD

18 / 100 page

AD9927

Rev. 0 | Page 18 of 100

H1 TO H8 PROGRAMMABLE EDGES:

1H1 RISING EDGE.

2H1 FALLING EDGE.

3H5 RISING EDGE.

4H5 FALLING EDGE.

H1, H3

H2, H4

H5, H7

H6, H8

Figure 19. HCLK Mode 3 Operation

P[0]

PIXEL

PERIOD

P[64] = P[0]

CCD

SIGNAL

P[32]

P[16]

P[48]

NOTES

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.

DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.

2. CONNECT H1, H3, H5, AND H7 TOGETHER AND H2, H4, H6, AND H8 TOGETHER FOR MAXIMUM DRIVE STRENGTH.

POSITION

H2, H4, H6, H8

RGr[0]

RGf[16]

HLr[0]

HLf[32]

H1, H3, H5, H7

H1r[0]

H1f[32]

SHP[32]

tS1

SHD[0]

Figure 20. High Speed Timing Default Locations

Digital Data Outputs

The AD9927 data output and DCLK phase are programmable

using the DOUTPHASE registers (Address 0x38, Bits [11:0]).

DOUTPHASEP (Bits [5:0]) selects any edge location from 0 to

63, as shown in Figure 21. DOUTPHASEN (Bits [11:6]) does

not actually program the phase of the data outputs but is used

internally and should always be programmed to a value of

DOUTPHASEP plus 32 edges. For example, if DOUTPHASEP

is set to 0, DOUTPHASEN should be set to 32 (0x20).

Normally, the DOUT and DCLK signals track in phase, based

on the contents of the DOUTPHASE registers. The DCLK output

phase can also be held fixed with respect to the data outputs by

changing the DCLKMODE register high (Address 0x38, Bit [12]).

In this mode, the DCLK output remains at a fixed phase equal

to a delayed version of CLI while the data output phase is still

programmable.

The pipeline delay through the AD9927 is shown in Figure 22.

After the CCD input is sampled by SHD, there is a 16-cycle

delay until the data is available.

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