AD9927BBCZ datasheet(74/100 Pages) AD

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AD9927

Rev. 0 | Page 74 of 100

Table 45. Power-Up Register Write Sequence

Address

Data

Description

0x10

0x01

Reset all registers to default values

0x26

User-

defined

Standby3 vertical output polarities

0x20 to

0xFFF

User-

defined

Horizontal, vertical, shutter timing

0xD8

0x888

Configure start-up register

0x00

0x04

Power-up the AFE, enables OB clamp

0x15

0x01

Starts CLO oscillator (if using crystal)

0x14

0x01

Starts internal timing core

0x20

0x01

Configure for master mode

0x11

0x01

Enable all outputs after SYNC

0x1C

0xFF8000

Configure sensor gate signals

0x13

0x4XX1

SWSYNC (if using software SYNC)

Using the SWSYNC Register

If an external SYNC pulse is not available, it is possible to

generate an internal SYNC in the AD9927 by writing 1 to the

SWSYNC register (Address 0x13, Bit [14]). If the software SYNC

option is used, the SYNC input (Pin D3) should be low (VSS)

during power-up. The SYNCENABLE register (Address 0x13,

Bit [0]) should be set high.

SYNC During Master Mode Operation

The hardware SYNC input can be used anytime during

operation to synchronize the AD9927 counters with external

timing, as shown in Figure 88. The operation of the digital

outputs can be suspended during the SYNC operation by

setting the SYNCSUSPEND register (Address 0x13, Bit [2]) to 1.

If SYNCSUSPEND = 1, the polarities of the outputs are held at

the same state as OUTCONTROL = low, as shown in Table 46.

Power-Up and Synchronization in Slave Mode

The power-up procedure for slave mode operation is the same

as the procedure for master mode operation with two exceptions:

•

Eliminate Step 8. Do not write the part into master mode.

•

No SYNC pulse is required in slave mode. Substitute

Step 10 with starting the external VD and HD signals.

This synchronizes the part, allows the register updates,

and starts the timing operation.

When the AD9927 is used in slave mode, the VD/HD inputs are

used to synchronize the internal counters. After a falling edge of

VD, there is a latency of 36 master clock CLI edges after the

falling edge of HD until the internal H-counter is reset. The

reset operation is shown in Figure 89.

Additional Restrictions in Slave Mode

When operating in slave mode, the following restrictions

should be noted:

•

The HD falling edge should be located in the same CLI

clock cycle as the VD falling edge, or later than the VD

falling edge. The HD falling edge should not be located

within five cycles prior to the VD falling edge.

•

If possible, all start-up serial writes should be performed

with VD and HD disabled. This prevents unknown

behavior caused by partial updating of registers before all

information is loaded.

SUSPEND

SYNC

H1 TO H4, RG,

XV1 TO XV24,

VSG, SUBCK

NOTES

1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0.

2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).

3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x13).

4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUTCONTROL = LOW.

5. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL THE SYNC RESET EDGE.

Figure 88. SYNC Timing to Synchronize the AD9927 with External Timing

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