AD9927BBCZ datasheet(72/100 Pages) AD

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AD9927

Rev. 0 | Page 72 of 100

POWER-UP SEQUENCE FOR MASTER MODE

When the AD9927 is powered up, the following sequence is

recommended (refer to Figure 87 for each step). Note that a

SYNC signal is required for master mode operation. If an

external SYNC pulse is not available, it is possible to generate an

internal SYNC event by writing to the SWSYNC register.

Turn on the power supplies for AD9927 and start the

master clock, CLI.

Reset the internal AD9927 registers by writing 1 to the

SW_RST register (Address 0x10).

By default, Vertical Outputs V1 to V24 are low. If

necessary, write to the Standby3 output polarity

(Address 0x26) to set different polarities for the vertical

outputs in order to avoid damage to the V-driver

and CCD. Write to Address 0x1C to configure each

V-output as a vertical transfer clock (XV) or sensor

pulse (VSG).

Power-up the V-driver supplies, VH and VL, anytime after

Step 3 is complete to set the proper polarities.

Load the required registers to configure the necessary

vertical timing, horizontal timing, high speed timing,

and shutter timing. Set the recommended start-up

Address 0xD8 to 0x888.

To place the part into normal power operation, write 0x04

to register 0x00. This sets the STANDBY register (AFE

enables the OB clamp (AFE Register Address 0x00, Bit [2]).

If the CLO output is being used to drive a crystal, also power

up the CLO oscillator by writing 1 to Address 0x15.

By default, the internal timing core is held in a reset state,

with TGCORE_RSTB register = 0. Write 1 to the

TGCORE_RSTB register (Address 0x14) to start the

internal timing core operation. Note if a 2× clock is used

for the CLI input, the CLIDIVIDE register (0x0D) should

be set to 1 before resetting the timing core.

Configure the AD9927 for master mode timing by writing 1

to the MASTER register (Address 0x20).

Write 1 to the OUTCONTROL register (Address 0x11).

This allows the outputs to become active after the next

SYNC rising edge. Normally OUTCONTROL takes effect

after the next VD edge; however, because the part is just

being powered up, there is no VD edge until the rising

edge of the SYNC signal. Write 0xFF8000 to the

VSGSELECT register to properly configure the sensor

gate signals.

10.

Generate a SYNC event. If SYNC is high at power-up,

bring the SYNC input low for a minimum of 100 ns, and

then bring SYNC high again. This causes the internal

counters to reset and starts VD/HD operation. The first

VD/HD edge allows VD-updated register updates to

occur, including OUTCONTROL to enable all outputs.

If a hardware SYNC is not available, the SWSYNC register

(Address 0x13, Bit [14]) can be used to initiate a SYNC event.

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