AD9927BBCZ datasheet(78/100 Pages) AD

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AD9927

Rev. 0 | Page 78 of 100

CIRCUIT LAYOUT INFORMATION

The PCB layout is critical in achieving good image quality from

the AD9927. All of the supply pins, particularly the AVDD,

TCVDD, RGVDD, and HVDD supplies, must be decoupled to

ground with good quality high frequency chip capacitors. The

decoupling capacitors should be located as close as possible to

the supply pins and should have a very low impedance path to a

continuous ground plane. If possible, there should be a 4.7 μF

or larger value bypass capacitor for each main supply—AVDD,

HVDD, and DRVDD—although this is not necessary for each

individual pin. In most applications, the supply for RGVDD

and HVDD is shared, which can be done as long as the

individual supply pins are separately bypassed with 0.1 μF

capacitors. A separate 3 V supply can also be used for DRVDD,

but this supply pin should still be decoupled to the same ground

plane as the rest of the chip. A separate ground for DRVSS is not

recommended.

The analog bypass pins (REFT and REFB) should be carefully

decoupled to ground as close as possible to their respective pins.

The analog input (CCDIN) capacitor should be located close to

the pin.

The H1 to H8, HL, and RG traces should be designed to have

low inductance to minimize distortion of the signals. The

complementary signals, H1/H3/H5/H7 and H2/H4/H6/H8,

should be routed as close together and as symmetrically as

possible to minimize mutual inductance. Heavier PCB traces

are recommended because of the large transient current

demand on H1 to H8 by the CCD. If possible, physically

locating the AD9927 closer to the CCD reduces the inductance

on these lines. As always, the routing path should be as direct as

possible from the AD9927 to the CCD.

Note that it is recommended that all H1 to H8 outputs on the

AD9927 be used together for maximum flexibility in drive

strength settings. A typical CCD with H1 and H2 inputs only

should have the AD9927’s H1, H3, H5, and H7 outputs connected

together to drive the CCD’s H1, and H2, H4, H6, and H8 outputs

connected together to drive the CCD’s H2. Similarly, a CCD

with H1, H2, H3, and H4 inputs should have the following:

• H1 and H3 connected to the CCD’s H1.

• H2 and H4 connected to the CCD’s H2.

• H5 and H7 connected to the CCD’s H3.

• H6 and H8 connected to the CCD’s H4.

Typical 3 V System

The AD9927 typical circuit connections for a 3 V system are

shown in Figure 94. This application uses an external 3.3 V

supply, which is connected to the AD9927’s LDO input. The

LDO is configured to output 1.8 V for the AD9927’s core supply

by connecting the LDO1P8EN pin to 3.3 V and the LDO3P2EN

pin to ground. The LDOOUT and SENSE pins are shorted

together and used to supply 1.8 V to the AVDD, TCVDD, and

DVDD pins.

Typical 1.8 V System

The internal LDO can be disabled by tying the LDO pins to

ground (LDOIN, LDO1P8EN, LDO3P2EN, LDOOUT, and

SENSE). In this case, an external 1.8 V regulator is required to

supply 1.8 V to the AVDD, TCVDD, and DVDD pins.

All of the AD9927’s remaining supplies can be directly supplied

with 1.8 V. The internal charge pump (CP) can be used to

generate 3.3 V for the H and RG supplies.

The AD9927 typical circuit connections for a 1.8 V system are

shown in Figure 95.

External Crystal Application

The AD9927 contains an on-chip oscillator for driving an

external crystal. Figure 96 shows an example application using a

typical 27 MHz crystal. For the exact values of the external

resistors and capacitors, it is best to consult the crystal

manufacturer’s data sheet.

Note that a 2× crystal is not recommended for use with the

CLO oscillator circuit. The crystal frequency should not exceed

40 MHz.

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