AD9927BBCZ datasheet(15/100 Pages) AD

15 / 100 page

AD9927

Rev. 0 | Page 15 of 100

SYSTEM OVERVIEW

Figure 13 shows the typical system block diagram for the AD9927

in master mode. The CCD output is processed by the AD9927’s

AFE circuitry, which consists of a CDS, VGA, black level clamp,

and ADC. The digitized pixel information is sent to the digital

image processor chip, which performs the postprocessing and

compression. To operate the CCD, all CCD timing parameters

are programmed into the AD9927 from the system microprocessor

through the 3-wire serial interface. From the master clock, CLI,

provided by the image processor or external crystal, the AD9927

generates the CCD’s horizontal and vertical clocks and internal

AFE clocks. External synchronization is provided by a sync

pulse from the microprocessor, which resets the internal

counters and resyncs the VD and HD outputs.

CCDIN

GPO1 TO GPO8

H1 TO H8, HL,

RG, VSUB

V1A TO V15, SUBCK

CCD

AD9927

AFETG

V-DRIVER

DIGITAL

IMAGE

PROCESSING

ASIC

DOUT

DCLK

HD, VD

CLI

SERIAL

INTERFACE

SYNC

µP

Figure 13. Typical System Block Diagram, Master Mode

Alternatively, the AD9927 can be operated in slave mode. In

this mode, the VD and HD are provided externally from the

image processor, and all AD9927 timing is synchronized with

VD and HD.

The H-drivers for H1 to H8, HL, and RG are included in the

AD9927, allowing these clocks to be directly connected to the

CCD. An H-driver voltage of up to 3.3 V is supported. V1A to

V15 and SUBCK vertical clocks are included as well, allowing

the AD9927 to provide all horizontal and vertical clocks

necessary to clock data out of a CCD.

The AD9927 includes programmable general-purpose outputs

(GPO), which can trigger mechanical shutter and strobe (flash)

circuitry.

Figure 14 and Figure 15 show the maximum horizontal and vertical

counter dimensions for the AD9927. All internal horizontal and

vertical clocking is controlled by these counters, which specify

line and pixel locations. Maximum HD length is 8192 pixels per

line, and maximum VD length is 8192 lines per field.

13-BIT HORIZONTAL = 8192 PIXELS MAX

13-BIT VERTICAL = 8192 LINES MAX

MAXIMUM COUNTER DIMENSIONS

Figure 14. Vertical and Horizontal Counters

MAX VD LENGTH IS 8192 LINES

CLI

MAX HD LENGTH IS 8192 PIXELS

Figure 15. Maximum VD/HD Dimensions

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