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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS47L35 датащи(PDF) 204 Page - Cirrus Logic |
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CS47L35 датащи(HTML) 204 Page - Cirrus Logic |
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204 / 300 page  204 DS1085F3 CS47L35 4.16 Clocking and Sample Rates 4.16.9.12Example FLL Settings Table 4-97 shows FLL settings for generating an oscillator frequency (FVCO) of 294.912 MHz from a variety of low- and high-frequency reference inputs. This is suitable for generating SYSCLK at 98.304 MHz and/or DSPCLK at 147.456 MHz. The recommended values of FLL1_PHASE_GAIN (0x2) and FLL1_CTRL_RATE (0x1) are also applicable in each case. Note that the FLL settings in Table 4-97 assume that the synchronizer is disabled. Table 4-97. Example FLL Settings—Synchronizer Disabled FLL (Main Loop) Settings FSOURCE FVCO (MHz) 1 1.FVCO =(FSOURCE/FREF Divider) × 3 × N.K × FRATIO FREF Divider 2 2.See Table 4-96 for the coding of the FLL1_REFCLK_DIV and FLL1_FRATIO fields. FRATIO 2 N.K 3 3.N.K values are represented in the FLL1_N, FLL1_THETA, and FLL1_LAMBDA fields. FLL1_N FLL1_ THETA FLL1_ LAMBDA FLL1_ GAIN FLL1_ PHASE_ ENA 32.000 kHz 294.912 1 4 768 0x300 0x0000 0x0001 0x2 1 32.768 kHz 294.912 1 3 1000 0x3E8 0x0000 0x0001 0x2 1 48 kHz 294.912 1 3 682.6667 0x2AA 0x0002 0x0003 0x0 0 128 kHz 294.912 1 1 768 0x300 0x0000 0x0001 0x2 1 512 kHz 294.912 1 1 192 0x0C0 0x0000 0x0001 0x2 1 1.536 MHz 294.912 1 1 64 0x040 0x0000 0x0001 0x3 1 3.072 MHz 294.912 1 1 32 0x020 0x0000 0x0001 0x3 1 11.2896 MHz 294.912 1 1 8.7075 0x008 0x0068 0x0093 0x5 0 12.000 MHz 294.912 1 1 8.192 0x008 0x0018 0x007D 0x5 0 12.288 MHz 294.912 1 1 8 0x008 0x0000 0x0001 0x3 1 13.000 MHz 294.912 1 1 7.5618 0x007 0x0391 0x0659 0x5 0 19.200 MHz 294.912 2 1 10.24 0x00A 0x0006 0x0019 0x5 0 24 MHz 294.912 2 1 8.192 0x008 0x0018 0x007D 0x5 0 26 MHz 294.912 2 1 7.5618 0x007 0x0391 0x0659 0x5 0 27 MHz 294.912 2 1 7.2818 0x007 0x013D 0x0465 0x5 0 |
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