CS47L35 datasheet(207/300 Pages) CIRRUS

207 / 300 page

DS1085F3

207

CS47L35

4.17 Control Interface

Continuous read and write modes enable multiple register operations to be scheduled faster than is possible with single

word, for as long as SS is held low and SCLK is toggled. Successive data words can be input/output every 16 (or 32) clock

cycles (depending on the applicable register address space).

The SPI protocol is shown in Fig. 4-66 and Fig. 4-67. Note that 16-bit data words are shown, but the equivalent protocol

also applies to 32-bit data words.

Fig. 4-66 shows a single register write to a specified address.

Figure 4-66. Control Interface SPI Register Write (16-Bit Data Words)

Fig. 4-67 shows a single register read from a specified address.

Figure 4-67. Control Interface SPI Register Read (16-Bit Data Words)

4.17.2 Two-Wire (I2C) Control Mode

The I2C control interface mode is supported on CIF2 only and uses the respective SCLK and SDA pins.

In I2C Mode, the CS47L35 is a slave device on the control interface; SCLK is a clock input, while SDA is a bidirectional

data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the CS47L35 transmits

Logic 1 by tristating the SDA pin, rather than pulling it high. An external pull-up resistor is required to pull the SDA line high

so that the Logic 1 can be recognized by the master.

In order to allow many devices to share a single two-wire control bus, every device on the bus has a unique 8-bit device

ID (this is not the same as the address of each register in the CS47L35).

The CS47L35 device ID is 0011_0100 (0x34). Note that the LSB of the device ID is the read/write bit; this bit is set to Logic

1 for read and Logic 0 for write.

The CS47L35 operates as a slave device only. The controller indicates the start of data transfer with a high-to-low

transition on SDA while SCLK remains high. This indicates that a device ID and subsequent address/data bytes follow.

The CS47L35 responds to the start condition and shifts in the next 8 bits on SDA (8-bit device ID, including read/write bit,

MSB first). If the device ID received matches the device ID of the CS47L35, the CS47L35 responds by pulling SDA low

on the next clock pulse (ACK). If the device ID is not recognized or the R/W bit is set incorrectly, the CS47L35 returns to

the idle condition and waits for a new start condition.

If the device ID matches the device ID of the CS47L35, the data transfer continues. The controller indicates the end of

data transfer with a low-to-high transition on SDA while SCLK remains high. After receiving a complete address and data

sequence the CS47L35 returns to the idle state and waits for another start condition. If a start or stop condition is detected

out of sequence at any point during data transfer (i.e., SDA changes while SCLK is high), the device returns to the idle

condition.

A30

MOSI

SCLK

31-bit register address

16-bit data word

R/W

A29

B14

B15

16-bit padding

A30

MOSI

SCLK

31-bit register address

16-bit data word

MISO

R/W

A29

B14

B15

16-bit padding

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