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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS47L35 датащи(PDF) 205 Page - Cirrus Logic |
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CS47L35 датащи(HTML) 205 Page - Cirrus Logic |
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205 / 300 page  DS1085F3 205 CS47L35 4.16 Clocking and Sample Rates Table 4-98 shows example FLL settings for generating an oscillator frequency (FVCO) of 294.912 MHz from a variety of low- and high-frequency reference inputs, with the synchronizer enabled. The main loop and the synchronizer loop must each be configured according to the respective input source. Note that, if the FLL synchronizer is enabled, the recommended settings for the main loop are not the same as those described in Table 4-97. Table 4-98. Example FLL Settings—Synchronizer Enabled FLL (Main Loop) Settings FSOURCE FVCO (MHz) 1 1.FVCO =(FSOURCE/FREF Divider) × 3 × N.K × FRATIO FREF Divider 2 2.See Table 4-96 for the coding of the FLL1_REFCLK_DIV and FLL1_FRATIO fields. FRATIO 2 N.K 3 3.N.K values are represented in the FLL1_N, FLL1_THETA, and FLL1_LAMBDA fields. FLL1_N FLL1_ THETA FLL1_ LAMBDA FLL1_ GAIN FLL1_ PHASE_ ENA 32.000 kHz 294.912 1 4 768 0x300 0x0000 0x0000 0x0 0 32.768 kHz 294.912 1 3 1000 0x3E8 0x0000 0x0000 0x0 0 48 kHz 294.912 1 3 682.6667 0x2AA 0xAAAA 0x0000 0x0 0 128 kHz 294.912 1 1 768 0x300 0x0000 0x0000 0x2 0 512 kHz 294.912 1 1 192 0x0C0 0x0000 0x0000 0x3 0 1.536 MHz 294.912 1 1 64 0x040 0x0000 0x0000 0x4 0 3.072 MHz 294.912 1 1 32 0x020 0x0000 0x0000 0x4 0 11.2896 MHz 294.912 1 1 8.7075 0x008 0xB51D 0x0000 0x5 0 12.000 MHz 294.912 1 1 8.192 0x008 0x3126 0x0000 0x5 0 12.288 MHz 294.912 1 1 8 0x008 0x0000 0x0000 0x5 0 13.000 MHz 294.912 1 1 7.5618 0x007 0x8FD5 0x0000 0x5 0 19.200 MHz 294.912 2 1 10.24 0x00A 0x3D70 0x0000 0x5 0 24 MHz 294.912 2 1 8.192 0x008 0x3126 0x0000 0x5 0 26 MHz 294.912 2 1 7.5618 0x007 0x8FD5 0x0000 0x5 0 27 MHz 294.912 2 1 7.2818 0x007 0x4822 0x0000 0x5 0 FLL (Synchronizer Loop) Settings FSOURCE FVCO (MHz) 4 4.FVCO =(FSOURCE/FSYNC Divider) × 3 × N.K × FRATIO FSYNC Divider 5 5.See Table 4-96 for the coding of the FLL1_SYNCCLK_DIV and FLL1_SYNC_FRATIO fields. FRATIO 5 N.K 6 6.N.K values are represented in the FLL1_SYNC_N, FLL1_SYNC_THETA, and FLL1_SYNC_LAMBDA fields. FLL1_ SYNC_N FLL1_ SYNC_ THETA FLL1_ SYNC_ LAMBDA FLL1_ SYNC_ GAIN FLL1_ SYNC_ DFSAT 32.000 kHz 294.912 1 16 192 0x0C0 0x0000 0x0001 0x0 1 32.768 kHz 294.912 1 16 187.5 0x0BB 0x0001 0x0002 0x0 1 48 kHz 294.912 1 16 128 0x080 0x0000 0x0001 0x0 1 128 kHz 294.912 1 4 192 0x0C0 0x0000 0x0001 0x0 0 512 kHz 294.912 1 2 96 0x060 0x0000 0x0001 0x2 0 1.536 MHz 294.912 1 1 64 0x040 0x0000 0x0001 0x4 0 3.072 MHz 294.912 1 1 32 0x020 0x0000 0x0001 0x4 0 11.2896 MHz 294.912 1 1 8.7075 0x008 0x0068 0x0093 0x4 0 12.000 MHz 294.912 1 1 8.192 0x008 0x0018 0x007D 0x4 0 12.288 MHz 294.912 1 1 8 0x008 0x0000 0x0001 0x4 0 13.000 MHz 294.912 1 1 7.5618 0x007 0x0391 0x0659 0x4 0 19.200 MHz 294.912 2 1 10.24 0x00A 0x0006 0x0019 0x4 0 24 MHz 294.912 2 1 8.192 0x008 0x0018 0x007D 0x4 0 26 MHz 294.912 2 1 7.5618 0x007 0x0391 0x0659 0x4 0 27 MHz 294.912 2 1 7.2818 0x007 0x013D 0x0465 0x4 0 |
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