CS47L35 datasheet(206/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.17 Control Interface

The CS47L35 is controlled by read/write access to its control registers. Two independent control interfaces are provided,

giving flexible capability as described below. Note that the SLIMbus interface also supports read/write access to the

CS47L35 control registers; see Section 4.10.

interface function can be supported with or without system clocking—there is no requirement for SYSCLK, or any other

system clock, to be enabled when accessing the register map.

The CS47L35 executes a boot sequence following power-on reset, hardware reset, software reset, or wake-up from Sleep

Mode. Note that control register writes should not be attempted until the boot sequence has completed. See Section 4.22

for further details.

A summary of the CS47L35 control interfaces is described in Table 4-99.

The CS47L35 provides an integrated pull-down resistor on the CIF1MISO pin. This provides a flexible capability for

interfacing with other devices. The pull-down is enabled by setting CIF1MISO_PD, as described in Table 4-100.

A detailed description of the I2C and SPI interface modes is provided in the following sections.

4.17.1 Four-Wire (SPI) Control Mode

The SPI control interface mode is supported on CIF1 only and uses the respective SS, SCLK, MOSI, and MISO pins.

In write operations (R/W = 0), the MOSI pin input is driven by the controlling device.

In read operations (R/W = 1), the MOSI pin is ignored following receipt of the valid register address.

If SS is asserted (Logic 0), the MISO output is actively driven when outputting data and is high impedance at other times.

If SS is not asserted, the MISO output is high impedance.

The high-impedance state of the MISO output allows the pin to be shared with other slaves. An internal pull-down resistor

can be enabled on the CIF1MISO pin, as described in Table 4-100.

Data transfers on CIF1 must use the applicable SPI message format, according to the register address space that is being

accessed:

• When accessing register addresses below R12288 (0x3000), the applicable SPI protocol comprises a 31-bit register

address and 16-bit data words.

• When accessing register addresses from R12888 (0x3000) upwards, the applicable SPI protocol comprises a 31-bit

• Note that, in all cases, the complete SPI message protocol also includes a read/write bit and a 16-bit padding phase

(see Fig. 4-66 and Fig. 4-67 below).

Table 4-99. CS47L35 Control Interface Summary

Control Interface

Description

Pin Functions

Power Domain

CIF1

Four-wire (SPI) interface CIF1MISO—Data output

CIF1MOSI—Data input

CIF1SCLK—Interface clock input

CIF1SS—Slave select input

DBVDD1

CIF2

Two-wire (I2C) interface CIF2SCLK—Interface clock input

CIF2SDA—Data input/output

DBVDD1

Table 4-100. Control Interface Pull-Down

Bit

Label

Default

Description

R8 (0x0008)

Ctrl_IF_CFG_1

CIF1MISO_PD

CIF1MISO Pull-Down Control

0 = Disabled

1 = Enabled

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