CS47L35 datasheet(139/300 Pages) CIRRUS

139 / 300 page

DS1085F3

139

CS47L35

4.11 Output Signal Path

Note that the SPKCLK frequencies noted in Table 4-65 assume that the SYSCLK frequency is a multiple of 6.144 MHz

(SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448 MHz (SYSCLK_FRAC = 1), the SPKCLK frequency

is scaled accordingly.

The output signal path control registers are defined in Table 4-66.

4.11.4 Output Signal Path Digital Volume Control

A digital volume control is provided on each of the output signal paths, providing –64 to +31.5 dB gain control in 0.5-dB

steps. An independent mute control is also provided for each output signal path.

Whenever the gain or mute setting is changed, the signal path gain is ramped up or down to the new settings at a

programmable rate. For increasing gain (or unmute), the rate is controlled by OUT_VI_RAMP. For decreasing gain (or

mute), the rate is controlled by OUT_VD_RAMP.

Note: The OUT_VI_RAMP and OUT_VD_RAMP fields should not be changed while a volume ramp is in progress.

The OUT_VU bits control the loading of the output signal path digital volume and mute controls. When OUT_VU is cleared,

the digital volume and mute settings are loaded into the respective control register, but does not actually change the signal

path gain. The digital volume and mute settings on all of the output signal paths are updated when a 1 is written to OUT_

VU. This makes it possible to update the gain of multiple signal paths simultaneously.

Note that, although the digital-volume controls provide 0.5-dB steps, the internal circuits provide signal gain adjustment in

0.125-dB steps. This allows a very high degree of gain control—smooth volume ramping under all operating conditions.

Note: The 0 dBFS level of the OUT5 digital output path is not equal to the 0 dBFS level of the CS47L35 digital core. The

maximum digital output level is –6 dBFS (see Table 3-8). Under 0 dB gain conditions, a 0 dBFS output from the

digital core corresponds to a –6 dBFS level in the PDM output.

The digital volume control registers are described in Table 4-67 and Table 4-68.

Table 4-65. SPKCLK Frequency

Condition

SPKCLK Frequency

OUT5_OSR = 0

3.072 MHz

OUT5_OSR = 1

6.144 MHz

Table 4-66. Output Signal Path Control

Label

Default

Description

R1024 (0x0400)

Output_Enables_1

15 EP_SEL

Output Path 1 Output Driver select

0 = HPOUTL and HPOUTR

1 = EPOUTP and EPOUTN

R1040 (0x0410)

Output_Path_

Config_1L

12 OUT1_MONO

Output Path 1 Mono Mode (Configures HPOUT and EPOUT as a mono differential output.)

0 = Disabled

1 = Enabled

The gain of the signal path is increased by 6 dB in differential (mono) mode.

R1072 (0x0430)

Output_Path_

Config_5L

13 OUT5_OSR

Output Path 5 Oversample Rate

0 = Normal mode

1 = High Performance mode

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