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CS47L35 датащи(PDF) 138 Page - Cirrus Logic |
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CS47L35 датащи(HTML) 138 Page - Cirrus Logic |
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138 / 300 page ![]() 138 DS1085F3 CS47L35 4.11 Output Signal Path 4.11.2 Output Signal Path Sample-Rate Control The output signal paths are derived from the respective output mixers within the CS47L35 digital core. The sample rate for the output signal paths is configured using OUT_RATE—see Table 4-21. Note that sample-rate conversion is required when routing the output signal paths to any signal chain that is configured for a different sample rate. 4.11.3 Output Signal Path Control The OUT1 path is associated with the headphone and the earpiece output drivers. The EP_SEL bit controls which of these outputs can be used—it is not possible to enable the headphone and earpiece drivers simultaneously. Under default register conditions, the OUT1 path is configured for stereo output. The path can be configured for mono differential (BTL) output using the OUT1_MONO bit; this is ideal for driving an earpiece or hearing aid coil. When the OUT1_MONO bit is set, the respective right channel output is an inverted copy of the left channel output signal; this creates a differential output between the respective outputs. The left and right channel output drivers must both be enabled in Mono Mode; both channels should be enabled simultaneously using the fields described in Table 4-64. The mono (BTL) signal paths are shown in Fig. 4-49. Note that, in Mono Mode, the effective gain of the signal path is increased by 6 dB. For stereo output on HPOUTL and HPOUTR, the required settings are as follows: • EP_SEL = 0 •OUT1_MONO = 0 For mono differential output on EPOUTP and EPOUTN, the required settings are as follows: • EP_SEL = 1 •OUT1_MONO = 1 Note that the EP_SEL and OUT1_MONO bits should not be changed while the headphone or earpiece drivers are enabled. These bits should be configured before enabling the respective drivers, and should remain unchanged until after the drivers have been disabled. The HPOUT and EPOUT drivers are enabled using the HP1L_ENA and HP1R_ENA bits, as described in Table 4-64. The SPKCLK frequency of the PDM output path (OUT5) is controlled by OUT5_OSR, as described in Table 4-65. When the OUT5_OSR bit is set, the audio performance is improved, but power consumption is also increased. R1025 (0x0401) Output_Status_1 9 OUT5L_ENA_STS 0 Output Path 5 (left) enable status 0 = Disabled 1 = Enabled 8 OUT5R_ENA_STS 0 Output Path 5 (right) enable status 0 = Disabled 1 = Enabled 7 OUT4L_ENA_STS 0 Output Path 4 (left) enable status 0 = Disabled 1 = Enabled R1030 (0x0406) Raw_Output_Status_1 1 OUT1L_ENA_STS 0 Output Path 1 (left) enable status 0 = Disabled 1 = Enabled 0 OUT1R_ENA_STS 0 Output Path 1 (right) enable status 0 = Disabled 1 = Enabled Table 4-64. Output Signal Path Enable (Cont.) Register Address Bit Label Default Description |
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