CS47L35 datasheet(137/300 Pages) CIRRUS

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DS1085F3

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CS47L35

4.11 Output Signal Path

4.11.1 Output Signal Path Enable

The output signal paths are enabled using the bits described in Table 4-64. The respective bits must be enabled for analog

or digital output on the respective output paths.

The OUT1 path is associated with the headphone and the earpiece output drivers. The HP1L_ENA and HP1R_ENA bits

control either the HPOUT or EPOUT drivers, depending on the EP_SEL register bit selection. See Table 4-66 for details

of the EP_SEL register.

The output signal paths are muted by default. It is recommended that deselecting the mute should be the final step of the

path enable control sequence. Similarly, the mute should be selected as the first step of the path disable control sequence.

The output signal path mute functions are controlled using the bits described in Table 4-64.

The supply rails for the OUT1 outputs (HPOUT and EPOUT) are generated using an integrated dual-mode charge pump,

CP1. The charge pump is enabled automatically by the CS47L35 when required by the output drivers; see Section 4.19.

The CS47L35 schedules a pop-suppressed control sequence to enable or disable the OUT1 and OUT4L signal paths.

This is automatically managed by the control-write sequencer in response to setting the respective HPnx_ENA or

SPKOUTL_ENA bits; see Section 4.18 for further details.

The output signal path enable/disable control sequences are inputs to the interrupt circuit and can be used to trigger an

interrupt event when a sequence completes; see Section 4.15.

The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The output signal paths

should be kept disabled (HP1x_ENA = 0, SPKOUTL_ENA = 0, OUT5x_ENA = 0) if SYSCLK is not enabled. See

Section 4.16 for details of the system clocks (including requirements for reconfiguring SYSCLK while audio paths are

enabled).

The CS47L35 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the output

signal paths and associated DACs. If the frequency is too low, an attempt to enable an output signal path fails. Note that

active signal paths are not affected under such circumstances.

The status bits in Register R1025 and R1030 indicate the status of each of the output signal paths. If an underclocked

error condition occurs, these bits indicate which signal paths have been enabled.

Table 4-64. Output Signal Path Enable

Bit

Label

Default

Description

R1024 (0x0400)

Output_Enables_1

9 OUT5L_ENA

Output Path 5 (left) enable

0 = Disabled

1 = Enabled

8 OUT5R_ENA

Output Path 5 (right) enable

0 = Disabled

1 = Enabled

7 SPKOUTL_ENA

Output Path 4 (left) enable

0 = Disabled

1 = Enabled

1 HP1L_ENA

Output Path 1 (left) enable

When EP_SEL = 0, this bit controls the HPOUTL output driver.

When EP_SEL = 1, this bit controls the EPOUTP output driver.

0 = Disabled

1 = Enabled

0 HP1R_ENA

Output Path 1 (right) enable

When EP_SEL = 0, this bit controls the HPOUTR output driver.

When EP_SEL = 1, this bit controls the EPOUTN output driver.

0 = Disabled

1 = Enabled

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