CS47L35 datasheet(134/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.11 Output Signal Path

Under normal operating conditions, the SLIMbus interface operates with a fixed root frequency (RF); dynamic updates to

the bus rate are applied using a selectable clock gear (CG) function. The root frequency and the clock gear setting are

controlled by the manager device; these parameters are transmitted in every SLIMbus superframe to all devices on the

bus.

In Gear 10 (the highest clock gear setting), the SLIMCLK input frequency is equal to the root frequency. In lower gears,

the SLIMCLK frequency is reduced by increasing powers of 2.

The clock gear definition is shown in Table 4-61.

Note: The 24.576-MHz root frequency is an example only; other frequencies are also supported.

The SLIMCLK input can be used to provide a reference source for the FLL. The frequency of this reference is controlled

using SLIMCLK_REF_GEAR, as described in Table 4-62.

The input clock reference for the FLL is selected by using FLL1_REFCLK_SRC. If SLIMbus is selected as the clock

source, the reference signal is generated using an adaptive divider on the SLIMCLK input. The divider automatically

adapts to the SLIMbus clock gear (CG). If the clock gear on the bus is lower than the SLIMCLK_REF_GEAR, the selected

reference frequency cannot be supported, and the SLIMbus clock reference is disabled.

See Section 4.16 for details of system clocking and the FLL.

4.11 Output Signal Path

The CS47L35 provides three audio output signal paths. These outputs comprise ground-referenced headphone/earpiece

drivers, differential speaker driver, and a digital output interface suitable for external speaker drivers. The output signal

paths are summarized in Table 4-63.

The analog output paths incorporate high performance 24-bit sigma-delta DACs.

Table 4-61. SLIMbus Clock Gear Selection

Clock Gear

Description

SLIMCLK Frequency 1

1.Assuming 24.576-MHz root frequency

Divide by 1

24.576 MHz

Divide by 2

12.288 MHz

Divide by 4

6.144 MHz

Divide by 8

3.072 MHz

Divide by 16

1.536 MHz

Divide by 32

768 kHz

Divide by 64

384 kHz

Divide by 128

192 kHz

Divide by 256

96 kHz

Divide by 512

48 kHz

Table 4-62. SLIMbus Clock Reference Control

Bit

Label

Default

Description

R1507 (0x05E3)

SLIMbus_Framer_

Ref_Gear

3:0

SLIMCLK_REF_

GEAR[3:0]

0x0

SLIMbus Clock Reference control. Sets the SLIMbus reference clock relative to

the SLIMbus Root Frequency (RF).

0x0 = Clock stopped

0x1 = Gear 1. (RF/512)

0x2 = Gear 2. (RF/256)

0x3 = Gear 3. (RF/128)

0x4 = Gear 4. (RF/64)

0x5 = Gear 5. (RF/32)

0x6 = Gear 6. (RF/16)

0x7 = Gear 7. (RF/8)

0x8 = Gear 8. (RF/4)

0x9 = Gear 9. (RF/2)

0xA = Gear 10. (RF)

All other codes are reserved

Table 4-63. Output Signal Path Summary

Signal Path

Descriptions

Output Pins

OUT1L, OUT1R

Ground-referenced headphone/earpiece output

HPOUTL, HPOUTR or EPOUTP, EPOUTN

OUT4L

Differential speaker output

SPKOUTN, SPKOUTP

OUT5L, OUT5R

Digital speaker (PDM) output

SPKDAT, SPKCLK

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