CS47L35 datasheet(115/300 Pages) CIRRUS

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DS1085F3

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CS47L35

4.7 Digital Audio Interface Control

4.7.2

AIF Pin Configuration

The external connections associated with each digital audio interface (AIF) are implemented on multi-function GPIO pins,

which must be configured for the respective AIF functions when required. The AIF connections are pin-specific alternative

functions available on specific GPIO pins. See Section 4.14 to configure the GPIO pins for AIF operation.

Integrated pull-up and pull-down resistors can be enabled on the AIFnLRCLK, AIFnBCLK and AIFnRXDAT pins. This is

provided as part of the GPIO functionality, and provides a flexible capability for interfacing with other devices. Each of the

pull-up and pull-down resistors can be configured independently using the fields described in Table 4-83.

If the pull-up and pull-down resistors are both enabled, the CS47L35 provides a bus keeper function on the respective pin.

The bus-keeper function holds the logic level unchanged whenever the pin is undriven (e.g., if the signal is tristated).

4.7.3

AIF Master/Slave Control

The digital audio interfaces can operate in master or slave modes and also in mixed master/slave configurations. In Master

Mode, the BCLK and LRCLK signals are generated by the CS47L35 when any of the respective digital audio interface

channels is enabled. In Slave Mode, these outputs are disabled by default to allow another device to drive these pins.

Master Mode is selected on the AIFnBCLK pin by setting AIFn_BCLK_MSTR. In Master Mode, the AIFnBCLK signal is

generated by the CS47L35 when one or more AIFn channels is enabled.

When the AIFn_BCLK_FRC bit is set in BCLK Master Mode, the AIFnBCLK signal is output at all times, including when

none of the AIFn channels is enabled. The AIFn_BCLK_FRC bit should be held at 0 if SYSCLK is not enabled. SYSCLK

must be present and enabled before setting the AIFn_BCLK_FRC bit. See Section 4.16.4 for further details (including

requirements for reconfiguring SYSCLK while AIF clock signals are enabled).

The AIFnBCLK signal can be inverted in master or slave modes using the AIFn_BCLK_INV bit.

Master Mode is selected on the AIFnLRCLK pin by setting AIFn_LRCLK_MSTR. In Master Mode, the AIFnLRCLK signal

is generated by the CS47L35 when one or more AIFn channels is enabled.

When AIFn_LRCLK_FRC is set in LRCLK Master Mode, the AIFnLRCLK signal is output at all times, including when none

of the AIFn channels is enabled. Note that AIFnLRCLK is derived from AIFnBCLK, and an internal or external AIFnBCLK

signal must be present to generate AIFnLRCLK. The AIFn_LRCLK_FRC bit should be held at 0 if SYSCLK is not enabled.

SYSCLK must be present and enabled before setting the AIFn_LRCLK_FRC bit. See Section 4.16.4 for further details

(including requirements for reconfiguring SYSCLK while AIF clock signals are enabled).

The AIFnLRCLK signal can be inverted in master or slave modes using the AIFn_LRCLK_INV bit.

The timing of the AIFnLRCLK signal is selectable using AIFn_LRCLK_ADV. If this bit is set, the LRCLK signal transition

is advanced to the previous BCLK phase (as compared with the default behavior). Further details of this option, and

conditions for valid use cases, are described in Section 4.7.3.1.

The AIF1 master/slave control registers are described in Table 4-35.

Table 4-35. AIF1 Master/Slave Control

Label

Default

Description

R1280 (0x0500)

AIF1_BCLK_Ctrl

7AIF1_

BCLK_INV

AIF1 Audio Interface BCLK Invert

0 = AIF1BCLK not inverted

1 = AIF1BCLK inverted

6AIF1_

BCLK_FRC

AIF1 Audio Interface BCLK Output Control

0 = Normal

1 = AIF1BCLK always enabled in Master Mode

5AIF1_

BCLK_

MSTR

AIF1 Audio Interface BCLK Master Select

0 = AIF1BCLK Slave Mode

1 = AIF1BCLK Master Mode

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