P5021 datasheet(111/155 Pages) NXP

111 / 155 page

Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

111

2.20.4.5

PCI Express AC physical layer specifications

This section contains the DC specifications for the physical layer of PCI Express on this device.

2.20.4.5.1

PCI Express AC physical layer transmitter specifications

This section discusses the PCI Express AC physical layer transmitter specifications 2.5 GT/s, and 5 GT/s.

This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential output at all transmitters. The parameters

are specified at the component pins. The AC timing specifications do not include RefClk jitter.

Table 66. PCI Express 2.0 (2.5 GT/s) differential transmitter Output AC specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max

Units

Notes

Unit interval

399.88

400

400.12

Each UI is 400 ps ± 300 ppm. UI does not

account for spread spectrum clock dictated

variations. See Note 1.

Minimum transmitter eye

width

TTX-EYE

0.75

—

The maximum transmitter jitter can be derived

as TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI.

Does not include spread spectrum or RefCLK

jitter. Includes device random jitter at 10-12.

See Notes 2 and 3.

Maximum time between the

jitter median and maximum

deviation from the median

TTX-EYE-MEDIAN-

to-

MAX-JITTER

—

0.125

Jitter is defined as the measurement variation

of the crossing points (VTX-DIFFp-p = 0 V) in

relation to a recovered transmitter UI. A

recovered transmitter UI is calculated over

3500 consecutive unit intervals of sample

data. Jitter is measured using all edges of the

250 consecutive UI in the center of the 3500 UI

used for calculating the transmitter UI.

See Notes 2 and 3.

AC coupling capacitor

CTX

—

200

All transmitters must be AC coupled. The AC

coupling is required either within the media or

within the transmitting component itself.

See Note 4.

Notes:

1. No test load is necessarily associated with this value.

2. Specified at the measurement point into a timing and voltage test load as shown in Figure 43 and measured over any 250

consecutive transmitter UIs.

3. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the

transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of

the total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It should be noted that the median is not

the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is

approximately equal as opposed to the averaged time value.

4. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.

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