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P5021 датащи(PDF) 114 Page - NXP Semiconductors |
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P5021 датащи(HTML) 114 Page - NXP Semiconductors |
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114 / 155 page ![]() P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Electrical characteristics Freescale Semiconductor 114 This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers (RXs). The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. 2.20.4.6 Test and measurement load The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be connected to the test/measurement load within 0.2 inches of that load, as shown in Figure 43. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the D+ and D– package pins. Figure 43. Test/Measurement load Table 69. PCI Express 2.0 (5 GT/s) differential receiver Input AC specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Units Notes Unit Interval UI 199.94 200.00 200.06 ps Each UI is 400 ps ±300 ppm. UI does not account for spread spectrum clock dictated variations. See Note 1. Max receiver inherent timing error TRX-TJ-CC — — 0.4 UI The maximum inherent total timing error for common RefClk receiver architecture Maximum time between the jitter median and maximum deviation from the median TRX-TJ-DC — — 0.34 UI Max receiver inherent total timing error Max receiver inherent deterministic timing error TRX-DJ-DD-CC — — 0.30 UI The maximum inherent deterministic timing error for common RefClk receiver architecture Max receiver inherent deterministic timing error TRX-DJ-DD-DC — — 0.24 UI The maximum inherent deterministic timing error for common RefClk receiver architecture Note: 1. No test load is necessarily associated with this value. Transmitter silicon + package C = CTX C = CTX R = 50 Ω R = 50 Ω D+ package pin D– package pin |
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