P5021 datasheet(90/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

Input setup

(for LGTA/LUPWAIT/LFRB)

tLBIVKL

6—

—

Input hold

(for LGTA/LUPWAIT/LFRB)

tLBIXKL

1—

—

Output delay

(Except LALE)

tLBKLOV

—1.5

—

Output hold

(Except LALE)

tLBKLOX

-3.5

—

Local bus clock to output high impedance

for LAD/LDP

tLBKLOZ

—2

LALE output negation to LAD/LDP output

transition (LATCH hold time)

tLBONOT

2 platform clock

cycles—1ns

(LBCR[AHD]=1)

—ns

4 platform clock

cycles—1ns

(LBCR[AHD]=0)

—

Notes:

1. All signals are measured from BVDD/2 of rising/falling edge of LCLK to BVDD/2 of the signal in question.

2. Skew measured between different LCLKs at BVDD/2.

3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current

delivered through the component pin is less than or equal to the leakage current specification.

4. tLBONOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBONOT is determined

by LBCR[AHD]. The unit is the eLBC controller clock cycle, which is the internal clock that runs the local bus controller, not

the external LCLK. LCLK cycle = eLBC controller clock cycle X LCRR[CLKDIV]. After power on reset, LBCR[AHD] defaults to

0 and eLBC runs at maximum hold time.

5. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK.

Table 49. Enhanced local bus timing specifications (continued)

For recommended operating conditions, see Table 3.

Parameter

Symbol1

Min

Max

Unit

Notes

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