P5021 datasheet(108/155 Pages) NXP

108 / 155 page

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

108

2.20.4

PCI Express

This section describes the clocking dependencies, DC and AC electrical specifications for the PCI Express bus.

2.20.4.1

Clocking dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all

times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.

2.20.4.2

PCI Express clocking requirements for SD_REF_CLKn and

SD_REF_CLKn

SerDes banks 1–2 (SD_REF_CLK[1:2] and SD_REF_CLK[1:2]) may be used for various SerDes PCI Express configurations

based on the RCW Configuration field SRDS_PRTCL. PCI Express is not supported on SerDes bank 3.

For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.”

2.20.4.3

PCI Express DC physical layer specifications

This section contains the DC specifications for the physical layer of PCI Express on this device.

2.20.4.3.1

PCI Express DC physical layer transmitter specifications

This section discusses the PCI Express DC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s.

This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all transmitters. The parameters

are specified at the component pins.

Table 62. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications

(XVDD = 1.5 V or 1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typical

Max

Units

Notes

Differential peak-to-peak

output voltage

VTX-DIFFp-p

800

—

1200

VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1.

De-emphasized differential

output voltage (ratio)

VTX-DE-RATIO

3.0

3.5

4.0

Ratio of the VTX-DIFFp-p of the second and

following bits after a transition divided by the

VTX-DIFFp-p of the first bit after a transition. See

Note 1.

DC differential transmitter

impedance

ZTX-DIFF-DC

100

120

Transmitter DC differential mode low Impedance

Transmitter DC impedance ZTX-DC

Required transmitter D+ as well as D– DC

Impedance during all states

Note:

1. Measured at the package pins with a test load of 50

Ω to GND on each pin.

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