P5021 datasheet(75/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 1.8 V.

2.10.2

eSPI AC timing specifications

This table provides the eSPI input and output AC timing specifications.

Table 28. eSPI DC electrical characteristics (CVDD = 1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

VIH

1.25

—

Input low voltage

VIL

—0.6

Input current (VIN = 0 V or VIN = CVDD)IIN

—±40

μA2

Output high voltage

(CVDD = min, IOH = –0.5 mA)

VOH

1.35

—

Output low voltage

(CVDD = min, IOL = 0.5 mA)

VOL

—0.4

—

Notes:

1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3.

2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

Table 29. eSPI AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol1

Min

Max

Unit Note

SPI_MOSI output—Master data (internal clock) hold time

tNIKHOX

2.36 +

(tPLATFORM_CLK *SP

MODE[HO_ADJ])

—

2, 3

SPI_MOSI output—Master data (internal clock) delay

tNIKHOV

—

5.24 +

(tPLATFORM_CLK *

SPMODE[HO_ADJ])

2, 3

SPI_CS outputs—Master data (internal clock) hold time

tNIKHOX2

0—

SPI_CS outputs—Master data (internal clock) delay

tNIKHOV2

—6.0

eSPI inputs—Master data (internal clock) input setup time

tNIIVKH

5—

—

eSPI inputs—Master data (internal clock) input hold time

tNIIXKH

0—

—

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI

outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid

(V).

2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

3. See the applicable chip reference manual for details on the SPMODE register.

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