P5021 datasheet(115/155 Pages) NXP

115 / 155 page

Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

115

2.20.5

XAUI

This section describes the DC and AC electrical specifications for the XAUI bus.

2.20.5.1

XAUI DC electrical characteristics

This section discusses the XAUI DC electrical characteristics for the clocking signals, transmitter, and receiver.

2.20.5.1.1

DC requirements for XAUI SD_REF_CLKn and SD_REF_CLKn

Only SerDes banks 2–3 (SD_REF_CLK[2:3] and SD_REF_CLK[2:3]) may be used for various SerDes XAUI configurations

based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported on SerDes bank 1.

For more information on these specifications, see Section 2.20.2.2, “DC-level requirement for SerDes reference clocks.”

2.20.5.1.2

XAUI transmitter DC electrical characteristics

This table defines the XAUI transmitter DC electrical characteristics.

2.20.5.1.3

XAUI receiver DC electrical characteristics

This table defines the XAUI receiver DC electrical characteristics.

2.20.5.2

XAUI AC timing specifications

This section discusses the XAUI AC timing specifications for the clocking signals, transmitter, and receiver.

Table 70. XAUI transmitter DC electrical characteristics (XVDD = 1.5 V or 1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Output voltage

–0.40

—

2.30

Differential output voltage

VDIFFPP

800

—

1600

mV p-p

—

Note:

1. Absolute output voltage limit

Table 71. XAUI receiver DC timing specifications (XVDD = 1.5 V or 1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Differential input voltage

VIN

200

900

1600

mV p-p

Note:

1. Measured at the receiver.

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