P5021 datasheet(17/155 Pages) NXP

17 / 155 page

Pin assignments and reset states

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

D2_MCS0

Chip Select

AC1

GVDD

—

D2_MCS1

Chip Select

AE1

GVDD

—

D2_MCS2

Chip Select

AB3

GVDD

—

D2_MCS3

Chip Select

AE2

GVDD

—

D2_MCKE0

Clock Enable

GVDD

—

D2_MCKE1

Clock Enable

GVDD

—

D2_MCKE2

Clock Enable

GVDD

—

D2_MCKE3

Clock Enable

GVDD

—

D2_MCK0

Clock

GVDD

—

D2_MCK1

Clock

GVDD

—

D2_MCK2

Clock

GVDD

—

D2_MCK3

Clock

GVDD

—

D2_MCK0

Clock Complements

GVDD

—

D2_MCK1

Clock Complements

GVDD

—

D2_MCK2

Clock Complements

GVDD

—

D2_MCK3

Clock Complements

GVDD

—

D2_MODT0

On Die Termination

AD2

GVDD

—

D2_MODT1

On Die Termination

AF1

GVDD

—

D2_MODT2

On Die Termination

AD1

GVDD

—

D2_MODT3

On Die Termination

AE3

GVDD

—

D2_MDIC0

Driver Impedance Calibration

AA4

I/O

GVDD

D2_MDIC1

Driver Impedance Calibration

I/O

GVDD

Local bus controller interface

LAD00

Muxed Data/Address

K26

I/O

BVDD

LAD01

Muxed Data/Address

L26

I/O

BVDD

LAD02

Muxed Data/Address

J26

I/O

BVDD

LAD03

Muxed Data/Address

H25

I/O

BVDD

LAD04

Muxed Data/Address

F25

I/O

BVDD

LAD05

Muxed Data/Address

H24

I/O

BVDD

LAD06

Muxed Data/Address

G24

I/O

BVDD

LAD07

Muxed Data/Address

G23

I/O

BVDD

LAD08

Muxed Data/Address

E23

I/O

BVDD

LAD09

Muxed Data/Address

D23

I/O

BVDD

LAD10

Muxed Data/Address

J22

I/O

BVDD

Table 1. Pins listed by bus (continued)

Signal

Signal description

Package

pin number

type

Power

supply

Notes

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