P5021 datasheet(57/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

This figure shows the undershoot and overshoot voltages at the interfaces of the chip.

Figure 7. Overshoot/Undershoot voltage for BVDD/GVDD/LVDD/OVDD

The core and platform voltages must always be provided at nominal 1.0 V or 1.2 V. See Table 3 for the actual recommended

core voltage conditions. Voltage to the processor interface I/Os is provided through separate sets of supply pins and must be

provided at the voltages shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage.

CVDD, BVDD, OVDD, and LVDD-based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type

specifications. The DDR SDRAM interface uses differential receivers referenced by the externally supplied MVREF signal

(nominally set to GVDD/2) as is appropriate for the SSTL_1.5 electrical signaling standard. The DDR DQS receivers cannot be

operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.

GND

GND – 0.3V

GND – 0.7 V

Not to Exceed 10%

Nominal C/X/B/G/L/OVDD + 20%

C/X/B/G/L/OVDD

C/X/B/G/L/OVDD + 5%

of tCLOCK

tCLOCK refers to the clock period associated with the respective interface:

VIH

VIL

Note:

For I2C, tCLOCK refers to SYSCLK.

For DDR GVDD, tCLOCK refers to Dn_MCK.

For eSPI CVDD, tCLOCK refers to SPI_CLK.

For eLBC BVDD, tCLOCK refers to LCLK.

For SerDes XVDD, tCLOCK refers to SD_REF_CLK.

For dTSEC LVDD, tCLOCK refers to EC_GTX_CLK125.

For JTAG OVDD, tCLOCK refers to TCK.

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