P5021 datasheet(3/155 Pages) NXP

номер детали	P5021

подробное описание детали	P5021 QorIQ Integrated Processor Data Sheet

PDF	155 Pages

Scroll/Zoom	100%

производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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Pin assignments and reset states

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

Figure 1. P5021 block diagram

Pin assignments and reset states

1.1

1295 FC-PBGA ball layout diagrams

These figures show the FC-PBGA ball map diagrams.

Real-time debug

18-Lane 5-GHz SerDes

512 KB

backside

L2 cache

Frame Manager

QorIQ P5021

Power Architecture®

e5500 Core

Security

5.0

eLBC

Queue

Mgr

Buffer

Mgr

eOpenPIC

Internal

Power mgmt

SD/MMC

SPI

2x DUART

4x I2Cs

Clocks/Reset

GPIO

CCSR

BootROM

2x USB 2.0

+ 2x PHY

Security

Monitor

PreBoot

Loader

32 KB

D-cache

32 KB

I-cache

1024 KB

frontside

L3 cache

64-bit

1600 MT/s DDR-3

memory controller

CoreNet™

Coherency Fabric

PAMU

Buffer

Parse, classify,

distribute

64-bit

1600 MT/s DDR-3

memory controller

1024 KB

frontside

L3 cache

PAMU

Perf

monitor

CoreNet

trace

Watchpoint

cross

trigger

Test

Port/

SAP

RAID5/6

DMA

10GE

1GE

1GE 1GE

Frame Manager

Buffer

Parse, classify,

distribute

1GE

1GE 1GE

1GE

10GE

PAMU

Peripheral access

management unit (PAMU)

SATA

SerDes

RGMII

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