P5021 datasheet(109/155 Pages) NXP

109 / 155 page

Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

109

This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential output at all transmitters. The parameters

are specified at the component pins.

2.20.4.4

PCI Express DC physical layer receiver specifications

This section discusses the PCI Express DC physical layer receiver specifications 2.5 GT/s, and 5 GT/s.

This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are

specified at the component pins.

Table 63. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications

(XVDD = 1.5 V or 1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typical

Max

Units

Notes

Differential peak-to-peak

output voltage

VTX-DIFFp-p

800

—

1200

VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1.

Low Power differential

peak-to-peak output voltage

VTX-DIFFp-p_low

400

500

1200

VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1.

De-emphasized differential

output voltage (ratio)

VTX-DE-RATIO-3.5dB

3.0

3.5

4.0

Ratio of the VTX-DIFFp-p of the second and

following bits after a transition divided by the

VTX-DIFFp-p of the first bit after a transition. See

Note 1.

De-emphasized differential

output voltage (ratio)

VTX-DE-RATIO-6.0dB

5.5

6.0

6.5

Ratio of the VTX-DIFFp-p of the second and

following bits after a transition divided by the

VTX-DIFFp-p of the first bit after a transition. See

Note 1.

DC differential transmitter

impedance

ZTX-DIFF-DC

100

120

Transmitter DC differential mode low

impedance

Transmitter DC Impedance ZTX-DC

Required transmitter D+ as well as D– DC

impedance during all states

Note:

1. Measured at the package pins with a test load of 50

Ω to GND on each pin.

Table 64. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (XVDD = 1.5 V or 1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max Units

Notes

Differential input peak-to-peak voltage

VRX-DIFFp-p

120

—

1200

VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-|

See Note 1.

DC differential input impedance

ZRX-DIFF-DC

100

120

Receiver DC differential mode

impedance.

See Note 2

DC input impedance

ZRX-DC

Required receiver D+ as well as D–

DC Impedance (50 ±20%

tolerance).

See Notes 1 and 2.

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