P5021 datasheet(66/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

This table provides the PLL lock times.

2.8

Power-on ramp rate

This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum

Power-On Ramp Rate is required to avoid falsely triggering the ESD circuitry. This table provides the power supply ramp rate

specifications.

2.9

DDR3 and DDR3L SDRAM controller

This section describes the DC and AC electrical specifications for the DDR3 and DDR3L SDRAM controller interface. Note

that the required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and GVDD(typ) voltage is 1.35 V when

interfacing to DDR3L SDRAM.

NOTE

When operating at DDR data rates of 1600 MT/s only one dual-ranked module per memory

controller is supported.

Input hold time for all POR configurations with respect to negation of

PORESET

—

SYSCLKs

Maximum valid-to-high impedance time for actively driven POR

configurations with respect to negation of PORESET

—

SYSCLKs

Notes:

1. SYSCLK is the primary clock input for the chip.

2. The device asserts HRESET as an output when PORESET is asserted to initiate the power-on reset process. The device

releases HRESET sometime after PORESET is negated. The exact sequencing of HRESET negation is documented in

Section 4.4.1 “Power-On Reset Sequence,” of the applicable chip reference manual.

3. PORESET must be driven asserted before the core and platform power supplies are powered up , see Section 2.2, “Power-up

sequencing.”

Table 16. PLL lock times

Parameter

Min

Max

Unit

Notes

PLL lock times

—

100

μs—

Table 17. Power supply ramp rate

Parameter

Min

Max

Unit

Notes

Required ramp rate for all voltage supplies (including OVDD/CVDD/

GVDD/BVDD/SVDD/XVDD/LVDD all VDD supplies, MVREF and all AVDD supplies.)

—

36000

V/s

1, 2

Notes:

1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of change

from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.

2. Over full recommended operating temperature range (see Table 3).

Table 15. RESET initialization timing specifications (continued)

Parameter

Min

Max

Unit1

Notes

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