P5021 datasheet(89/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

2.14.2

Enhanced local bus AC timing specifications

This section describes the AC timing specifications for the enhanced local bus interface.

2.14.2.1

Test condition

This figure provides the AC test load for the enhanced local bus.

Figure 23. Enhanced local bus AC test load

2.14.2.2

Local bus AC timing specification

All output signal timings are relative to the falling edge of any LCLKs. The external circuit must use the rising edge of the

LCLKs to latch the data.

All input timings except LGTA/LUPWAIT/LFRB are relative to the rising edge of LCLKs. LGTA/LUPWAIT/LFRB are relative

to the falling edge of LCLKs.

This table describes the timing specifications of the local bus interface.

Input current (VIN = 0 V or VIN = BVDD)IIN

—±40

μA2

Output high voltage

(BVDD = min, IOH = –0.5 mA)

VOH

1.35

—

Output low voltage

(BVDD = min, IOL = 0.5 mA)

VOL

—0.4

—

Notes:

1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3.

2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.”

Table 49. Enhanced local bus timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

—

Local bus duty cycle

tLBKH/tLBK

—

LCLK[n] skew to LCLK[m]

tLBKSKEW

—150

Input setup

(except LGTA/LUPWAIT/LFRB)

tLBIVKH

6—

—

Input hold

(except LGTA/LUPWAIT/LFRB)

tLBIXKH

1—

—

Table 48. Enhanced local bus DC electrical characteristics (BVDD = 1.8 V) (continued)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

BVDD/2

RL = 50 Ω

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