P5021 datasheet(61/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

This table shows the estimated power dissipation on the AVDD and AVDD_SRDS supplies for the chip’s PLLs, at allowable

voltage levels.

Typical

1800

600

1200

450

1.0

1.1

—

Thermal

105

———

—

Maximum

2.2

Notes:

1. Combined power of VDD_PL, VDD_CA, SVDD with both DDR controllers and all SerDes banks active. Does not include I/O

power.

2. Typical power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform with

90% activity factor.

3. Typical power based on nominal processed device.

4. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and executing DMA on the platform

at 100% activity factor.

5. Thermal power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform at

90% activity factor.

6. Maximum power provided for power supply design sizing.

7. Thermal and maximum power are based on worst case processed device.

Table 7. AVDD power dissipation

AVDDs

Typical

Maximum

Unit

Notes

AVDD_DDR

515

AVDD_CC1

515

AVDD_CC2

515

AVDD_PLAT

515

AVDD_FM

515

AVDD_SRDS1

—36

AVDD_SRDS2

—36

AVDD_SRDS3

—36

AVDD_SRDS4

—36

USB_VDD_1P0

—

VDD_LP

—5

Note:

1. VDD_CA = 1.2 V, TA = 80°C, TJ = 105°C

2. VDD_PL, SVDD = 1.0 V, TA = 80°C, TJ = 105°C

3. USB_VDD_1P0, VDD_LP = 1.0 V, TA = 80°C, TJ = 105°C

Table 6. Power dissipation (continued)

Power

Mode

Core

freq

(MHz)

Plat

freq

(MHz)

DDR

data

rate

(MHz)

FM freq

(MHz)

VDD_PL,

SVDD

(V)

VDD_CA

(V)

Junction

temp

(

°C)

Core

and plat-

form

power1

(W)

VDD_PL

power

(W)

VDD_CA

power

(W)

SVDD

power

(W)

Note

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