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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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P5021 датащи(PDF) 19 Page - NXP Semiconductors |
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P5021 датащи(HTML) 19 Page - NXP Semiconductors |
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19 / 155 page  Pin assignments and reset states P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 19 LCS4 Chip Selects D22 O BVDD 5 LCS5 Chip Selects B23 O BVDD 5 LCS6 Chip Selects F24 O BVDD 5 LCS7 Chip Selects G26 O BVDD 5 LWE0 Write Enable D24 O BVDD — LWE1 Write Enable A24 O BVDD — LWE2 Write Enable J16 O BVDD — LWE3 Write Enable K15 O BVDD — LBCTL Buffer Control C22 O BVDD — LALE Address Latch Enable A23 I/O BVDD — LGPL0/LFCLE UPM General Purpose Line 0/ LFCLE—FCM B25 O BVDD 3, 4 LGPL1/LFALE UPM General Purpose Line 1/ LFALE—FCM E25 O BVDD 3, 4 LGPL2/LOE/LFRE UPM General Purpose Line 2/ LOE_B—Output Enable D25 O BVDD 3, 4 LGPL3/LFWP UPM General Purpose LIne 3/ LFWP_B—FCM H26 O BVDD 3, 4 LGPL4/LGTA/LUPWAIT/LPBSE UPM General Purpose Line 4/ LGTA_B—FCM C25 I/O BVDD 39 LGPL5 UPM General Purpose Line 5 / Amux E26 O BVDD 3, 4 LCLK0 Local Bus Clock C24 O BVDD — LCLK1 Local Bus Clock C23 O BVDD — DMA DMA1_DREQ0/GPIO18 DMA1 Channel 0 Request AP21 I OVDD 26 DMA1_DACK0/GPIO19 DMA1 Channel 0 Acknowledge AL19 O OVDD 26 DMA1_DDONE0 DMA1 Channel 0 Done AN21 O OVDD 27 DMA2_DREQ0/GPIO20/ALT_MDVAL DMA2 Channel 0 Request AJ20 I OVDD 26 DMA2_DACK0/EVT7/ALT_MDSRCID0 DMA2 Channel 0 Acknowledge AG19 O OVDD 26 DMA2_DDONE0/EVT8/ALT_MDSRCID1 DMA2 Channel 0 Done AP20 O OVDD 26 USB Port 1 USB1_UDP USB1 PHY Data Plus AT27 I/O USB_VDD_ 3P3 — USB1_UDM USB1 PHY Data Minus AT26 I/O USB_VDD_ 3P3 — USB1_VBUS_CLMP USB1 PHY VBUS Divided Signal AK25 I USB_VDD_ 3P3 38 Table 1. Pins listed by bus (continued) Signal Signal description Package pin number Pin type Power supply Notes |
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