P5021 datasheet(56/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

Input voltage

DDR3 and DDR3L DRAM

signals

MVIN

GND to GVDD

DDR3 and DDR3L DRAM

reference

MVREF

GVDD/2 ± 1%

Ethernet signals (except EMI2)

LVIN

GND to LVDD

eSPI, eSHDC

CVIN

GND to CVDD

Enhanced local bus signals

BVIN

GND to BVDD

DUART, I2C, DMA, MPIC, GPIO,

system control and power

management, clocking, debug,

I/O voltage select, and JTAG I/O

voltage

OVIN

GND to OVDD

SerDes signals

SVIN

GND to SVDD

USB PHY Transceiver signals

USB_VIN_3P3

GND to

USB_VDD_3P3

Ethernet Management interface

2 (EMI2) signals

—

GND to 1.2V

4, 7

Operating Temperature range

Normal Operation

TA,

TA = 0 (min) to

TJ = 105 (max)

(90 (max) core

frequency > 2000

MHz)

°C—

Extended Temperature

TA,

TA = -40 (min) to

TJ = 105 (max)

°C—

Secure Boot Fuse Programming

TA,

TA = 0 (min) to

TJ = 70 (max)

°C2

Notes:

1. VDD_PL voltage must not exceed VDD_CA.

2. POVDD must be supplied 1.5 V and the chip must operate in the specified fuse programming temperature range only

during secure boot fuse programming. For all other operating conditions, POVDD must be tied to GND, subject to the

power sequencing constraints shown in Section 2.2, “Power-up sequencing.”

3. Selecting RGMII limits LVDD to 2.5V.

4. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage

levels. LVDD must be powered to use this interface.6. Supply voltage specified at the voltage sense pin. Voltage input

pins must be regulated to provide specified voltage at the sense pin.

7. All input signals must increase/decrease monotonically throughout the entire rise/fall duration.

Table 3. Recommended operating conditions (continued)

Parameter

Symbol

Recommended

value

Unit

Notes

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