P5021 datasheet(83/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

2.12.3.3

Ethernet management interface 1 AC timing specifications

This table provides the Ethernet management interface 1 AC timing specifications.

2.12.3.4

Ethernet management interface 2 AC electrical characteristics

This table provides the Ethernet management interface 2 AC timing specifications.

Output low voltage (IOL = 100 μA)

VOL

—0.2

—

Output low current (VOL = 0.2 V)

IOL

4—

—

Input capacitance

CIN

—10

—

Table 40. Ethernet management interface 1 AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol1

Min

Typ

Max

Unit

Note

MDC frequency

fMDC

——

2.5

MHz

MDC clock pulse width high

tMDCH

160

—

MDC to MDIO delay

tMDKHDX

(16

× t

plb_clk) – 6

—

(16

× t

plb_clk) + 6

3, 4

MDIO to MDC setup time

tMDDVKH

8—

—

MDIO to MDC hold time

tMDDXKH

0—

—

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes

management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or

data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D)

reaching the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of

the MgmtClk Clock EC_MDC).

3. This parameter is dependent on the frame manager clock frequency. The delay is equal to 16 frame manager clock periods

±6 ns. For example, with a frame manager clock of 333 MHz, the min/max delay is 48 ns ± 6 ns. Similarly, if the frame

manager clock is 400 MHz, the min/max delay is 40 ns ± 6 ns.

4. tplb_clk is the frame manager clock period.

Table 41. Ethernet management interface 2 AC timing specifications

For recommended operating conditions, see Table 3.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Note

MDC frequency

fMDC

——

2.5

MHz

MDC clock pulse width high

tMDCH

160

—

MDC to MDIO delay

tMDKHDX

(0.5 ×(1/fMDC)) – 6

—

(0.5 ×(1/fMDC)) + 6

MDIO to MDC setup time

tMDDVKH

8—

—

Table 39. Ethernet management interface 2 DC electrical characteristics (1.2 V) (continued)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Max

Unit

Note

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