P5021 datasheet(106/155 Pages) NXP

106 / 155 page

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

106

2.20.2.3

AC requirements for SerDes reference clocks

This table lists AC requirements for the PCI Express, SGMII, Serial RapidIO and Aurora SerDes reference clocks to be

guaranteed by the customer’s application design.

Figure 40. Differential measurement points for rise and fall time

Table 61. SD_REF_CLKn and SD_REF_CLKn input clock requirements (SVDD = 1.0 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

SD_REF_CLK/SD_REF_CLK frequency range

tCLK_REF

—

100/125

—

MHz

SD_REF_CLK/SD_REF_CLK clock frequency

tolerance

tCLK_TOL

–350

—

350

ppm

—

SD_REF_CLK/SD_REF_CLK reference clock duty

cycle

tCLK_DUTY

SD_REF_CLK/SD_REF_CLK max deterministic

peak-peak jitter at 10-6 BER

tCLK_DJ

—

SD_REF_CLK/SD_REF_CLK total reference clock

jitter at 10-6 BER (peak-to-peak jitter at refClk input)

tCLK_TJ

—

SD_REF_CLK/SD_REF_CLK rising/falling edge rate

tCLKRR/tCLKFR

1—4

V/ns

Differential input high voltage

VIH

200

—

Differential input low voltage

VIL

—

–200

Rising edge rate (SD_REF_CLKn) to falling edge rate

(SD_REF_CLKn) matching

Rise-Fall

Matching

——

5, 6

Notes:

1. Caution: Only 100 and 125 have been tested. In-between values not work correctly with the rest of the system.

2. Limits from PCI Express CEM Rev 2.0

3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn). The

signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is

centered on the differential zero crossing. See Figure 40.

4. Measurement taken from differential waveform

5. Measurement taken from single-ended waveform

6. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV

window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross

point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate

of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not

exceed 20% of the slowest edge rate. See Figure 41.

VIH = +200 mV

VIL = –200 mV

0.0 V

SD_REF_CLKn

–

SD_REF_CLKn

Fall Edge Rate

Rise Edge Rate

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