P5021 datasheet(104/155 Pages) NXP

104 / 155 page

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

104

The characteristics of the clock signals are as follows:

•

The SerDes transceivers core power supply voltage requirements (SVDD) are as specified in Section 2.1.2,

“Recommended operating conditions.”

•

The SerDes reference clock receiver reference circuit structure is as follows:

—The SD_REF_CLKn and SD_REF_CLKn are internally AC-coupled differential inputs as shown in Figure 36.

Each differential clock input (SD_REF_CLKn or SD_REF_CLKn) has on-chip 50-

Ω termination to SGND

followed by on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

— The SerDes reference clock input can be either differential or single-ended. See the differential mode and

single-ended mode descriptions below for detailed requirements.

•

The maximum average current requirement also determines the common mode voltage range.

— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the

maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage

is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input

is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V

÷ 50 = 8 mA)

while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle

can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such

that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode

voltage at 400 mV.

— If the device driving the SD_REF_CLKn and SD_REF_CLKn inputs cannot drive 50

Ω to SGND DC or the drive

strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled off-chip.

•

The input amplitude requirement is described in detail in the following sections.

2.20.2.2

DC-level requirement for SerDes reference clocks

The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect

the clock driver chip and SerDes reference clock inputs, as described below:

•

Differential Mode

— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or

between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have

a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external

DC-coupled or AC-coupled connection.

— For an external DC-coupled connection, as described in Section 2.20.2.1, “SerDes reference clock receiver

characteristics,” the maximum average current requirements sets the requirement for average voltage (common

mode voltage) as between 100 mV and 400 mV. Figure 37 shows the SerDes reference clock input requirement

for DC-coupled connection scheme.

Figure 37. Differential reference clock input DC requirements (external DC-coupled)

SD_REF_CLKn

Vmax

< 800 mV

Vmin

> 0V

100 mV

< Vcm < 400 mV

200 mV < Input Amplitude or Differential Peak < 800 mV

P5021 датащи(PDF) 104 Page - NXP Semiconductors

P5021 датащи(HTML) 104 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL